Control system for a dynamic random access memory and method of operation thereof

• US 20070195631A1
• Filed: 02/21/2006
• Published: 08/23/2007
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hoffmann, Jochen
• Granted Patent: US 7,453,758 B2
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.

Claims

1. A dynamic random access memory device comprising:

an array of dynamic random access memory cells subdivided into a group of blocks;

at least one group of sense amplifiers coupled to each block of memory cells; and

a decoder coupled to the array of memory cells, wherein each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.

2. The device of claim 1, further comprising a plurality of latches operable to store mode information for each block of memory cells.

3. The device of claim 2, wherein the mode information includes information relating to whether the block is in the single cell mode, the twin cell mode or a transition between single cell mode and twin cell mode.

4. The device of claim 2, further comprising a control register coupled to the latches, the control register operable to receive user information indicating that at least one of the blocks is to be programmed into the single cell mode or the twin cell mode.

5. The device of claim 2, further comprising control circuitry coupled to the latches, the control circuitry programming the latches to cause at least one of the blocks to operate in the single cell mode or the twin cell mode, the control circuitry being formed on a semiconductor substrate and the array of memory cells is also formed on the semiconductor substrate.

6. The device of claim 1, further comprising a refresh-pulse generating circuit coupled to the decoder, the refresh-pulse generating causing a block of the array to be refreshed at a first rate if the block is in the single cell mode and at a second rate if the block is in the twin cell mode.

7. The device of claim 6, wherein the refresh-pulse generating circuit comprises an oscillator coupled to a counter, the counter being coupled to the decoder.

8. A dynamic random access memory device comprising:

an array of dynamic random access memory cells subdivided into a group of blocks; and

means for independently causing each block of memory cells to be operated in either a single cell mode or a twin cell mode.

9. The device of claim 8, wherein the means for independently causing each block of memory cells to be operated in either a single cell mode or a twin cell mode is coupled to receive information from outside the dynamic random access memory device, the information indicating whether a particular block or blocks should be operated in the single cell mode and/or the twin cell mode.

10. The device of claim 8, wherein the means for independently causing each block of memory cells to be operated in either a single cell mode or a twin cell mode comprises means for selecting a mode of operation based on address locations of accesses that are requested.

11. The device of claim 10, wherein the means for selecting are formed on a semiconductor substrate and wherein the array of dynamic random access memory cells are also formed on the semiconductor substrate.

12. The device of claim 8, further comprising means for scrambling addresses in such a way that a transition between operating modes is executed concurrently with a user-requested access.

13. A method of operating a dynamic random access memory (DRAM) device that includes memory cells organized in a plurality of blocks, the method comprising:

storing data in a first block of memory cells, the data being stored in the first block in a single cell mode; and

storing data in a second block of memory cells, the data being stored in the second block in a twin cell mode, wherein the second block stores data in the twin cell mode at the same time the first block stores data in the twin cell mode.

14. The method of claim 13, further comprising performing a refresh operation, wherein the reference operation refreshes cells of the first block at a first refresh rate and refreshes cells of the second block at a second refresh rate that is longer than the first refresh rate.

15. The method of claim 13, further comprising:

storing data in a third block of memory cells, the data being stored in the third block in a first mode; and

transitioning the third block to store the data in a second mode, wherein the first mode comprises one of the single cell mode or the twin cell mode and the second mode comprises the other of the single cell mode or the twin cell mode.

16. A method of operating a dynamic random access memory device, the method comprising:

providing an array of dynamic random access memory cells arranged in a plurality of blocks; and

storing data in ones of the blocks of memory cells, wherein the data is stored in either a single cell mode or a twin cell mode as a function of the block.

17. The method of claim 16, further comprising receiving mode information, the mode information determining whether a particular block of the plurality of blocks stores data in the single cell mode or the twin cell mode.

18. The method of claim 17, wherein the mode information is received from an external controller.

19. The method of claim 17, wherein the mode information is determined by circuitry on-chip with the array of dynamic random access memory cells.

20. The method of claim 16, wherein storing data in ones of the blocks of memory cells comprises operating in an adaptive mode in which the device selects a mode of operation based upon address-locations of accesses that are requested.

21. The method of claim 16, wherein, during a sleep mode, each of the blocks of memory cells is operated in the twin cell mode.

22. A method of operating a digital recording device, the method comprising:

recording a digital image;

storing the recorded digital image in a dynamic random access memory, the recorded digital image being stored in a single cell mode;

processing the recorded digital image; and

storing the processed digital image in the dynamic random access memory, the processed digital image being stored in a twin cell mode.

23. The method of claim 22, wherein storing the recorded digital image comprises transferring data from a charge-coupled device to the dynamic random access memory in an uncompressed fashion.

24. The method of claim 22, further comprising transmitting the processed digital image from the dynamic random access memory.

25. The method of claim 24, further comprising causing the dynamic random access memory to transition from the twin cell mode to the single cell mode prior to transmitting the processed digital image.

26. The method of claim 22, wherein, prior to recording the digital image, the method further comprises:

receiving an indication that an image is to be recorded; and

causing the dynamic random access memory to transition from the twin cell mode to the single cell mode.

27. The method of claim 22, wherein storing the recorded digital image in the dynamic random access memory comprises storing the recorded digital image in a portion of the dynamic random access memory, wherein the recorded digital image is stored in the single cell mode while other portions of the dynamic random access memory store data in the twin cell mode.