Pipelined packet switching and queuing architecture
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Abstract
An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet'"'"'s routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
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Citations
50 Claims
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1-20. -20. (canceled)
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21. An apparatus for switching packets, each packet having a header and a corresponding tail, the apparatus comprising:
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a header processing pipeline comprising a plurality of pipeline stage circuits connected in a sequence, wherein the plurality of pipeline stage circuits comprises at least a fetch stage circuit and a gather stage circuit;
an input buffer configured to receive a multicast packet header from a switch fabric interface queue;
sequence number logic configured to associate a first sequence number with the multicast packet header; and
a recycle path coupling the gather stage circuit and the fetch state circuit, wherein the fetch stage circuit is configured to provide the multicast packet header and first sequence number to a subsequent stage circuit in the header processing pipeline, and the gather stage circuit is configured to output the first sequence number and a modified multicast packet header corresponding to the multicast packet header, and provide a multicast packet header replica to the fetch stage circuit via the recycle path. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An apparatus for switching packets, each packet having a header and a corresponding tail, the apparatus comprising:
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means for receiving a multicast packet header;
means for associating a first sequence number with the multicast packet header;
means for fetching the multicast packet header comprising means for providing the multicast packet header and the first sequence number to a subsequent one of a plurality of sequential means for processing;
means for outputting a modified multicast packet header and the first sequence number from an egress means for processing of the plurality of sequential means for processing; and
means for providing a multicast packet header replica to the means for fetching from the egress means for processing, wherein the modified multicast packet header corresponds to the multicast packet header, and the multicast packet header replica is a replica of the multicast packet header. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. A method for switching packets comprising:
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receiving a multicast packet header;
associating a first sequence number with the multicast packet header;
providing the multicast packet header and first sequence number to a first stage circuit of a header processing pipeline, wherein the header processing pipeline comprises a plurality of pipeline stage circuits connected in sequence;
processing the multicast packet header in one or more of the stages of the header processing pipeline and generating a modified multicast packet header corresponding to the multicast packet header;
outputting the modified multicast packet header and the first sequence number; and
providing a multicast packet header replica to the first stage circuit of the header processing pipeline, wherein the multicast packet header replica is a replica of the multicast packet header. - View Dependent Claims (45, 46, 47, 48, 49, 50)
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Specification