NROM NON-VOLATILE MODE OF OPERATION

• US 20070196982A1
• Filed: 08/02/2006
• Published: 08/23/2007
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Granted Patent: US 7,692,961 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Claims

1. A method for operating a plurality of NVM memory cells comprising:

performing a first programming step using hot hole injection (HHI) to reduce the threshold voltage (Vt) of selected ones of the memory cells; and

performing a second programming step using channel hot electron (CHE) injection to increase the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in first programming step.

2. The method of claim 1, wherein the NVM cells are NROM cells.

3. The method of claim 1, wherein:

each memory cell has two charge-trapping areas; and

each charge-trapping area of a memory cell is capable of storing at least one bit.

4. The method of claim 1, wherein, for operating on a given bit of an NROM cell comprising a first (source) terminal, a gate, and a second (drain) terminal:

in the first programming step;

the first terminal is set to approximately 2 volts;

the gate is set to approximately −

8 volts;

the second terminal is set to approximately 4 volts;

in the second programming step;

the first terminal is set to ground (0 v).

the gate is set to approximately 9.5 volts; and

the second terminal is set to approximately 4.5 volts.

5. The method of claim 4, wherein, in all of the three (erase, first programming, second programming) steps:

a substrate voltage (Vb) is maintained at 0 volts (0 v).

6. The method of claim 1, wherein:

the HHI programming step is performed using pulses, separated by reads; and

the CHE programming step is performed with pulses, separated by reads.

7. The method of claim 1, wherein:

the plurality of memory cells comprise a sector; and

the sector size is 128 kilobytes (KB) to 1 megabyte (MB).

9. The method of claim 7, wherein:

the step (a) is performed using Hot Hole Injection (HHI); and

the step (b) is performed using Channel Hot Electron (CHE) injection.

8. A method for programming a plurality of memory cells, each cell having a characteristic program voltage (PV) and a characteristic erase voltage (EV), the method comprising the steps of:

(a) programming first selected ones of the cells by decreasing the threshold voltage of the first selected ones of the cells to less than the program voltage (Vt<

PV); and

(b) refreshing second selected ones of the cells by increasing the threshold voltage (Vt) of the cells to greater than the erase voltage (Vt>

EV).

10. A method of programming a NVM memory cell comprising:

using a combination of hot hole injection (HHI), followed by channel hot electron (CHE).

11. The method of claim 10, wherein:

the memory cell is an NROM memory cell.

12. The method of claim 10, wherein:

the memory cell has two charge-trapping areas; and

each charge-trapping area is capable of storing at least one bit.

13. The method of claim 10, wherein:

the method comprises comprise Page Write only with HHI and CHE for programming, without any erase.