Poly pre-doping anneals for improved gate profiles

• US 20070196988A1
• Filed: 02/23/2006
• Published: 08/23/2007
• Est. Priority Date: 02/23/2006
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hall, Mark, Grudowski, Paul, Stephens, Tab, Adetutu, Olubunmi, Shroff, Mehul, Stout, Phillip
• Application Number:
  US11/360,796
• Publication Number:
  US 20070196988A1
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

Claims

1. A method for forming a semiconductor device comprising:

providing a semiconductor substrate;

forming a gate dielectric layer over the semiconductor substrate;

forming an undoped gate electrode layer over the gate dielectric layer;

implanting a first implant species into the gate electrode layer in a first circuit area;

heating the gate electrode layer at a selected temperature using rapid thermal annealing to anneal the first implant species so that subsequent etching of the gate electrode layer creates an etched gate having substantially vertical sidewalls; and

selectively etching the gate electrode layer to form an etched gate having substantially vertical sidewalls.

2. The method of claim 1, comprising implanting a first dopant species into the gate electrode layer in the first circuit area prior to selectively etching the gate electrode layer.

3. The method of claim 2, where implanting the gate electrode layer with a first implant species comprises implanting nitrogen to an average depth in the gate electrode layer that is below an average depth of the implanted first dopant species.

4. The method of claim 2, further comprising implanting a second dopant species into the gate electrode layer in a second circuit area before heating the gate electrode layer.

5. The method of claim 1, where heating the gate electrode layer comprises heating the gate electrode layer at a temperature between approximately 700-1100°

C. for between 5-60 seconds.

6. The method of claim 1, where heating the gate electrode layer comprises heating the gate electrode layer at a temperature between approximately 800-1000°

C.

7. The method of claim 1, where heating the gate electrode layer comprises heating the gate electrode layer in the presence of a gas selected from the group consisting of nitrogen, helium, oxygen and argon.

8. The method of claim 1, where the first implant species comprises nitrogen, xenon or germanium.

9. The method of claim 1, further comprising heating the gate electrode layer with a spike anneal after using rapid thermal annealing.

10. The method of claim 1, where heating the gate electrode layer comprises a spike anneal process.

11. The method of claim 1, where the undoped gate electrode layer comprises a layer of intrinsic polysilicon.

12. The method of claim 1, where the substantially vertical sidewalls have substantially no hour-glassing.

13. A method for forming a gate electrode, comprising:

depositing an intrinsic polysilicon layer over a gate dielectric layer formed over a substrate;

implanting a first species into the polysilicon layer in a first circuit area;

implanting a first dopant species into the polysilicon layer in the first circuit area;

implanting a second species into the polysilicon layer in a second circuit area;

then

annealing the polysilicon layer, first species, first dopant species and second dopant species at a selected temperature so that subsequent etching of the polysilicon layer creates an etched gate electrode having substantially vertical sidewalls; and

selectively etching the polysilicon layer to form an etched gate electrode having substantially vertical sidewalls.

14. The method of claim 13, where annealing the polysilicon layer comprises heating the polysilicon layer at a temperature between approximately 800-1000°

C. for between 5-60 seconds.

15. The method of claim 13, where heating the polysilicon layer comprises heating the polysilicon layer in the presence of an inert gas selected from the group consisting of nitrogen, helium and argon.

16. The method of claim 13, where annealing the polysilicon layer comprises a rapid thermal anneal or spike anneal process.

17. The method of claim 13, where implanting a first species comprises implanting nitrogen to an average depth in the polysilicon layer that is below an average depth of the first dopant species.

18. A method of fabricating a polysilicon device feature comprising:

implanting at least part of an undoped polysilicon layer with a diffusion retardation species and a dopant species;

applying one or more rapid thermal anneal processes to anneal the implanted diffusion retardation species; and

then

etching the polysilicon layer to form a polysilicon device feature having substantially vertical sidewalls.

19. The method of claim 18, further comprising implanting a second part of the undoped polysilicon layer with a second dopant species prior to applying one or more rapid thermal anneal processes.

20. The method of claim 18, further comprising implanting a second part of the undoped polysilicon layer with a second dopant species after applying one or more rapid thermal anneal processes.