Nitride semiconductor component and process for its production

• US 20070197004A1
• Filed: 12/20/2006
• Published: 08/23/2007
• Est. Priority Date: 02/23/2006
• Status: Active Grant

• Current Assignee: AZUR SPACE Solar Power GmbH (5N Plus, Inc.)
• Original Assignee: ALLOS Semiconductors GmbH
• Inventors: Dadgar, Armin, Krost, Alois
• Granted Patent: US 9,406,505 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

The invention relates to a process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising the steps:

• • provision of a substrate that has a silicon surface;
  • deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate;
  • optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer;
  • deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer;
  • deposition of a gallium-containing first nitride semiconductor layer on the masking layer,
    wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm² in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Claims

1. Process for the production of a layer structure of a nitride semiconductor component on a silicon surface, including the steps:

provision of a substrate that has a silicon surface;

deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate;

optional;

deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer;

deposition of a masking layer on the nitride nucleation layer or, where present, on the first nitride buffer layer;

deposition of a gallium-containing first nitride semiconductor layer on the masking layer,

wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μ

m² in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

2. Process according to claim 1, in which the masking layer is deposited in a layer thickness that in the first nitride semiconductor layer, which initially grows in the form of growth islands, leads to a layer area that is at least 80% closed from a distance of, on average, at least 600 nm from the masking layer.

3. Process according to claim 1, in which the masking layer is deposited with a coverage of the underlying nitride nucleation layer or, if present, of the first nitride buffer layer, of at least 95%.

4. Process according to claim 1, in which the masking layer is deposited from silicon nitride.

5. Process according to claim 1, in which the duration of the deposition of the masking layer is chosen so that in the deposition step of the first nitride semiconductor layer a concomitant measurement of the reflection intensity of the growth surface at a light wavelength of ca. 600 nm shows an oscillating intensity behaviour with increasing oscillation amplitude, which after at least 5 oscillation cycles reaches a maximum value that then remains roughly constant.

6. Process according to claim 1s, in which the deposition of the nitride nucleation layer takes place on a (111) silicon surface.

7. Process according to claim 1, in which the first nitride semiconductor layer is deposited in a layer thickness of between 800 nm and 1600 nm.

8. Process according to claim 7, in which an aluminium-containing nitride intermediate layer is deposited on the first nitride semiconductor layer and in which a gallium-containing, further, second nitride semiconductor layer is deposited on the last layer.

9. Process according to claim 8, in which the sequence of steps of the deposition of an aluminium-containing nitride intermediate layer and a gallium-containing further nitride semiconductor layer are carried out repeatedly.

10. Process according to claim 8, in which a multi-quantum-well structure of nitride semiconductor material is deposited on the further nitride semiconductor layer.

11. Process according to claim 10, characterised by the deposition of at least one further masking layer of silicon nitride immediately before the deposition of those of the further nitride semiconductor layers on which the multi-quantum-well structure is deposited.

12. Process according to claim 1, in which an n-doping is introduced into the first and, if present, those further nitride semiconductor layers that are deposited before the multi-quantum-well structure.

13. Process according to claim 1, comprising the following steps:

production of a p-doped, gallium-containing nitride semiconductor cover layer on the multi-quantum-well structure.

14. Process according to claim 1, in which the step of providing a substrate includes the provision of a silicon substrate, the thickness of which is at least D_GaN×

x, wherein D_GaN denotes the layer thickness of the nitride semiconductor layer to be deposited on the substrate or, if more than one nitride semiconductor layer is to be deposited, denotes the sum of the layer thicknesses of the nitride semiconductor layers to be deposited on the substrate and of the existing nitride intermediate layer, and wherein x in the case where a doped silicon substrate is used is 110 and in the case where an undoped substrate is used is 200.

15. Process according to claim 14, in which the step of providing a substrate includes the provision of a silicon substrate, the thickness of which is additionally greater than or equal to 100×

√

{square root over (D_GaN)}×

y, where

16. Process for the production of a nitride semiconductor component, comprising the steps:

production of a layer structure of a nitride semiconductor component on a silicon surface according to claim 1;

bonding of the layer structure to a carrier in such a way that the growth upper side of the layer structure is facing the carrier;

either complete or partial removal of the substrate;

production of a contact structure.

17. Process according to claim 16, with a step involving the deposition of an electrically conducting contact layer on the growth upper side of the layer structure.

18. Process according to claim 17, in which for the contact layer a material is used that has a higher refractive index than the p-doped nitride semiconductor cover layer.

19. Process according to one of claim 16, with a step, carried out before the bonding, involving metallisation of the growth upper side of the layer structure or, if present, of the contact layer.

20. Process according to claim 16, in which a carrier is used whose surface that is employed for the bonding is electrically conducting or reflecting or metallic.

21. Process according to claim 18, in which the nitride semiconductor cover layer of the layer structure is deposited in a thickness of

22. Process according to claim 17, in which a material is used for the contact layer that has a smaller refractive index than the p-doped nitride semiconductor cover layer.

23. Process according to claim 22, in which the nitride semiconductor cover layer of the layer structure is deposited in a thickness of

24. Process according to one of claim 16 in which the bonding is carried out at a temperature in the range between 280 and 500°

C.

25. Process according to one of claim 16, in which the step of removing the substrate is carried out by grinding or by combined grinding and etching.

26. Process according to claim 16, in which the step of removing the substrate is carried out solely by etching.

27. Process according to claim 16, in which the growth rear side exposed by the removal of the substrate is structured for the formation of an anti-reflection-acting layer.

28. Nitride semiconductor component with

a gallium-containing first nitride semiconductor layer that has a structure of coalesced crystallites that occupy an average surface area of at least 0.16 μ

m² in a layer plane perpendicular to the growth direction,

an aluminium-containing nitride intermediate layer that adjoins the first nitride semiconductor layer, and

a gallium-containing further, second nitride semiconductor layer adjoining the last layer.

29. Nitride semiconductor component according to claim 28, in which the crystallites in a layer plane perpendicular to the growth direction have an average size of at least 400×

400 nm².

30. Nitride semiconductor component according to claim 28, in which the crystallites in a layer plane perpendicular to the growth direction occupy an average surface area of at least 0.36 μ

m².

31. Nitride semiconductor component according to claim 28, in which the first nitride semiconductor layer has a layer thickness of between 800 nm and 1600 nm.

32. Nitride semiconductor component according to claim 28, that repeatedly contains the layer sequence of aluminium-containing nitride intermediate layer and gallium-containing further nitride semiconductor layer.

33. Nitride semiconductor component according to claim 31, in which a multi-quantum-well structure of nitride semiconductor material is deposited on the further nitride semiconductor layer.

34. Nitride semiconductor component according to claim 33, characterised by at least one further masking layer of silicon nitride immediately adjoining that layer of the further nitride semiconductor layers on which the multi-quantum-well structure is deposited, but on the side of this further nitride semiconductor layer facing away from the multi-quantum-well structure.

35. Nitride semiconductor component according to claim 28, in which the first and, where present, those further nitride semiconductor layers that are arranged on the side of the multi-quantum-well structure that faces towards the first nitride semiconductor layer, are n-doped.

36. Nitride semiconductor component according to claim 33, with a p-doped, gallium-containing nitride semiconductor cover layer that is arranged on the side of the multi-quantum-well structure facing away from the first nitride semiconductor layer.

37. Nitride semiconductor component according to claim 28, with a carrier that is bonded to the first nitride semiconductor layer.

38. Nitride semiconductor component according to claim 28, in which the carrier and the first nitride semiconductor layer are bonded to one another via a metal layer.

39. Nitride semiconductor component according to claim 37, in which the carrier consists primarily of copper or aluminium or silicon or aluminium nitride or of Al/Si.

40. Nitride semiconductor component according to claim 28, in which an electrically conducting contact layer is arranged between the carrier and the first nitride semiconductor layer.

41. Nitride semiconductor component according to claim 40, in which the contact layer has a higher refractive index than the p-doped nitride semiconductor cover layer.

42. Nitride semiconductor component according to claim 36, in which the nitride semiconductor cover layer of the layer structure is deposited in a thickness of

43. Nitride semiconductor component according to claim 40, in which the contact layer has a lower refractive index than the p-doped nitride semiconductor cover layer.

44. Nitride semiconductor component according to claim 43, in which the nitride semiconductor cover layer of the layer structure is deposited in a thickness of

45. Nitride semiconductor component according to one of claim 28, with an n-side and a p-side electrical contact element.

46. Carrier wafer with a plurality of nitride semiconductor components according to claim 28.

47. Carrier wafer according to claim 46, in which the plurality of nitride semiconductor components on the carrier have in totality a lateral dimension of at least 24 cm.

48. Nitride semiconductor product with

a substrate that has a silicon surface,

an aluminium-containing nitride nucleation layer adjoining the silicon surface,

optional:

an aluminium-containing nitride buffer layer adjoining the nitride nucleation layer,

a masking layer on the nitride nucleation layer or, if present, on the nitride buffer layer, and with

a gallium-containing first nitride semiconductor layer arranged adjoining the masking layer and having a structure of coalesced crystallites, in which the crystallites above a coalescence layer thickness and in a layer plane perpendicular to the growth direction occupy an average surface area of at least 0.16 μ

m².

49. Nitride semiconductor product according to claim 48, in which the growth islands have coalesced in an amount of at least 80% at a distance of at least 600 nm from the masking layer.

50. Nitride semiconductor product according to claim 48, in which the nitride nucleation layer is an aluminium nitride layer or an aluminium/gallium nitride layer with an aluminium proportion of at least 10%.

51. Nitride semiconductor product according to claim 50, in which the nitride nucleation layer has a layer thickness of between 10 and 100 nm.

52. Nitride semiconductor product according to claim 48, in which the nitride buffer layer has a layer thickness of at most 400 nm.

53. Nitride semiconductor product according to claim 48, in which the substrate in a direction perpendicular to the rear side substrate surface is either free of curvature or has a radius of curvature of at least 10 m.

54. Nitride semiconductor product according to claim 48, with an aluminium-containing nitride intermediate layer that adjoins the first nitride semiconductor layer and,

with a gallium-containing further, second nitride semiconductor layer adjoining the last layer.

55. Nitride semiconductor product according to claim 48, in which the crystallites in a layer plane perpendicular to the growth direction occupy an average surface area of at least 0.36 μ

m².

56. Nitride semiconductor product according to claim 48, in which the substrate has a lateral dimension of at least 24 cm.