Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration

• US 20070197011A1
• Filed: 02/22/2006
• Published: 08/23/2007
• Est. Priority Date: 02/22/2006
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Srivastava, Anadi, Jawarani, Dharmesh, Grudowski, Paul, Mora, Rode
• Application Number:
  US11/360,318
• Publication Number:
  US 20070197011A1
• Time in Patent Office: Days
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer

Abstract

A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a lateral portion of the gate. An implant region (215) is then created adjacent to the spacer, and a layer of silicide (225) is formed which extends over the exposed lateral portion of the gate.

Claims

1. A method for making a silicided gate structure, comprising:

providing a semiconductor substrate having a gate disposed thereon and having a spacer disposed adjacent to the gate;

subjecting the spacer to a recess etch which exposes a lateral portion of the gate;

creating an implant region adjacent to the spacer; and

forming a layer of silicide over the exposed lateral portion of the gate.

2. The method of claim 1, wherein the layer of silicide also extends over a portion of the substrate adjacent to the spacer structure.

3. The method of claim 1, wherein the layer of silicide is formed by depositing a conformal layer of a refractory metal such that the conformal layer is in contact with the first and second lateral portions of the gate.

4. The method of claim 3, wherein the refractory metal is selected from the group consisting of Co, Ti, Ni, and NiSi.

5. The method of claim 1, wherein the layer of silicide comprises cobalt silicide.

6. The method of claim 1, wherein the gate has a dielectric layer disposed thereon which separates the spacer from the gate, and wherein the recess etch removes any exposed portion of the dielectric layer.

7. The method of claim 6, wherein the step of creating an implant region adjacent to the spacer involves implanting a dopant into a substrate adjacent to the spacer, and wherein the implantation is aligned with the spacer.

8. The method of claim 7, wherein the device has first and second implant regions in the substrate, wherein the second implant region is formed by an implantation that occurs after the recess etch and that is aligned with the spacer, and wherein the first implant region is formed by an implantation that is aligned with the gate.

9. The method of claim 8, wherein the recess etch reduces the width of the spacer.

10. The method of claim 8, wherein said first and second implant regions form the source and drain regions of a transistor.

11. The method of claim 8, wherein the first and second implant regions are each formed by implantation of a dopant followed by diffusion.

12. The method of claim 1, wherein the recess etch is selective to the material of the gate.

13. The method of claim 12, wherein a dielectric layer is disposed between the spacer and the gate, and wherein the recess etch also etches the dielectric layer.

14. The method of claim 1 wherein, prior to the recess etch, the spacer covers the entire side of the electrode.

15. A method for making a silicided gate structure, comprising:

providing a semiconductor substrate having a gate disposed thereon;

depositing a conformal layer of spacer material over the gate;

subjecting the conformal layer to a first etch so as to define first and second spacer structures therein, wherein the first and second spacer structures are adjacent to the gate;

subjecting the first spacer to a second etch which exposes a first lateral portion of the gate;

creating first and second implant regions adjacent to the first and second spacers; and

forming a layer of silicide over the first lateral portion of the gate.

16. The method of claim 15, wherein the second spacer is subjected to the second etch so as to expose a second lateral portion of the gate, and wherein the step of forming a layer of silicide over the first lateral portion of the gate further involves forming the layer of silicide over the second lateral portion of the gate.

17. The method of claim 15, wherein the layer of silicide also extends over a portion of the substrate adjacent to the first and second spacer structures.

18. The method of claim 15, wherein the layer of silicide is formed by depositing a conformal layer of a refractory metal such that the conformal layer is in contact with the first and second lateral portions of the gate.

19. The method of claim 18, wherein the refractory metal is selected from the group consisting of Co, Ti, Ni, and NiSi.

20. The method of claim 15, wherein the layer of silicide comprises cobalt silicide.