Enhanced data integrity using parallel volatile and non-volatile transfer buffers

• US 20070198796A1
• Filed: 02/22/2006
• Published: 08/23/2007
• Est. Priority Date: 02/22/2006
• Status: Active Grant

• Current Assignee: Maersk Incorporated (A.P. Møller Holding A/S), Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Warren, Robert
• Granted Patent: US 7,549,021 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11B 5/09 Digital recording

Abstract

Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block for subsequent transfer to a downstream block, such as a data storage array. The controller is further configured to direct second data to the second volatile memory block for subsequent transfer to the non-volatile circular buffer. Preferably, the second volatile memory block forms a portion of a non-volatile random access memory (NVRAM) and the circular buffer is formed from a flash memory device. An intelligence block preferably controls said subsequent transfer of the second data from the second volatile memory block to the circular buffer. The second data are preferably transferred from the circular buffer to the downstream block in conjunction with the transfer of the first data.

Claims

1. An apparatus comprising a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block for subsequent transfer to a downstream block, and to direct second data to the second volatile memory block for subsequent transfer to the non-volatile circular buffer.

2. The apparatus of claim 1, further comprising a mechanism to provide the second volatile memory block with non-volatile retention of data written to said second volatile memory block in the event of an interruption of supply power to said second volatile memory block.

3. The apparatus of claim 1, wherein the second volatile memory block composes a portion of a non-volatile random access memory (NVRAM).

4. The apparatus of claim 1, wherein at least a selected one of the first and second volatile memory blocks comprises a dynamic random access memory (DRAM).

5. The apparatus of claim 1, wherein at least a selected one of the first and second volatile memory blocks comprises a static random access memory (SRAM).

6. The apparatus of claim 1, wherein the circular buffer is characterized as a flash memory device.

7. The apparatus of claim 1, wherein the second volatile memory block is characterized as a first-in-first-out (FIFO) queue so that blocks of data written in a selected sequence to the second volatile memory block are transferred in said sequence to the circular buffer.

8. The apparatus of claim 1, wherein the first and second data each respectively comprise user data addressable by a host device using respective logical block addresses (LBAs).

9. The apparatus of claim 1, wherein the controller is further configured to transfer the second data from the circular buffer to the downstream block concurrently with the transfer of the first data from the first volatile memory block to the downstream block.

10. The apparatus of claim 1, further comprising an intelligence block which controls said subsequent transfer of the second data from the second volatile memory block to the circular buffer.

11. The apparatus of claim 10, wherein the intelligence block appends an error correction code to the second data transferred from the second volatile memory block to the circular buffer.

12. The apparatus of claim 1, wherein the controller is further configured to, in response to a data retrieval request for a selected set of data, check for a cache hit for said selected set of data from the first volatile memory block, and check for a cache hit for said selected set of data from the circular buffer.

13. An apparatus comprising:

a controller;

a volatile memory block configured to receive a selected data block pending subsequent transfer of said data to a downstream block; and

first means in parallel with the volatile memory block for alternatively storing said data block in a non-volatile circular buffer.

14. The apparatus of claim 13, wherein the first means comprises a second volatile memory block.

15. The apparatus of claim 14, wherein the first means further comprises a mechanism to provide the second volatile memory block with non-volatile retention of data written to said second volatile memory block in the event of an interruption of supply power to said second volatile memory block.

16. A method comprising:

using a controller to direct first data to a first volatile memory block for subsequent transfer to a downstream block; and

using the controller to direct second data to a second volatile memory block for subsequent transfer to a non-volatile circular buffer.

17. The method of claim 16, comprising a subsequent step of transferring the second data from the non-volatile circular buffer to the storage array.

18. The method of claim 17, wherein the transferring step is carried out in conjunction with the first using step so that both the first and second data are concurrently transferred to the storage array.

19. The method of claim 16, further comprising a step of providing a mechanism to provide the second volatile memory block with non-volatile retention of data written to said second volatile memory block in the event of an interruption of supply power to said second volatile memory block.

20. The method of claim 16, wherein the downstream block comprises a storage array.