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SECURE PROCESSOR

  • US 20070198851A1
  • Filed: 07/10/2006
  • Published: 08/23/2007
  • Est. Priority Date: 02/22/2006
  • Status: Active Grant
First Claim
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1. A secure processor, which decrypts an encrypted instruction code and executes the instruction code, comprising:

  • a processor core for executing the instruction code obtained by decrypting the encrypted instruction code;

    a secure bus implemented in the position where the program executed by the processor core cannot access to; and

    a secure hardware connected to the secure bus, for performing authentication of the encrypted instruction code executed using the processor core and performing encryption/decryption of the encrypted instruction code and data that the processor core inputs from/outputs to the outside.

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