ELECTROSTATIC PROTECTION DEVICE FOR SEMICONDUCTOR CIRCUIT FOR DECREASING INPUT CAPACITANCE

• US 20070200140A1
• Filed: 02/23/2007
• Published: 08/30/2007
• Est. Priority Date: 02/24/2006
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Jang Hoo
• Application Number:
  US11/678,121
• Publication Number:
  US 20070200140A1
• Time in Patent Office: Days
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An electrostatic protection device for a semiconductor circuit for protecting an internal circuit from static electricity applied to the pad includes a first conductivity type semiconductor substrate; second conductivity type diffusion regions formed on the surface of the semiconductor substrate at regular intervals into a dot type; isolation structures formed on the surface of the semiconductor substrate to respectively surround the second conductivity type diffusion regions; and first conductivity type diffusion regions formed on the surface of the semiconductor substrate outside of the second conductivity type diffusion regions and the isolation regions.

Claims

1. An electrostatic protection device for a semiconductor circuit for protecting an internal circuit from static electricity applied to a pad, comprising:

a first conductivity type semiconductor substrate;

second conductivity type diffusion regions formed on the surface of the semiconductor substrate at regular intervals into a dot type;

isolation structures formed on the surface of the semiconductor substrate to respectively surround the second conductivity type diffusion regions; and

first conductivity type diffusion regions formed on the surface of the semiconductor substrate outside of the second conductivity type diffusion regions and the isolation regions.

2. The device according to claim 1, wherein each second conductivity type diffusion region has the sectional shape of a polygon with corners each having an angle greater than 90°

.

3. The device according to claim 2, wherein each second conductivity type diffusion region has the sectional shape of an octagon.

4. The device according to claim 1, wherein each second conductivity type diffusion region has the sectional shape of a quadrangle having rounded corners.

5. The device according to claim 1, wherein the distance between two second conductivity type diffusion regions, which adjoin each other in a widthwise direction thereof, is less than the width of each second conductivity type diffusion region.

6. The device according to claim 1, further comprising:

first lines formed to be connected to the first conductivity type diffusion regions; and

second lines formed to be connected to the second conductivity type diffusion regions.

7. The device according to claim 6, further comprising:

a connection line located between the first conductivity type diffusion regions and the first lines, and formed to have the shape of a matrix; and

connection patterns located between the second conductivity type diffusion regions and the second lines.

8. The device according to claim 6, wherein the first lines are connected to a ground line or a source voltage supply line.

9. The device according to claim 6, wherein the second lines are connected to the pad.

10. The device according to claim 6, further comprising:

a plurality of first contacts formed on the first conductivity type diffusion regions and connected to the first lines; and

a plurality of second contacts formed on the second conductivity type diffusion regions and connected to the second lines.

11. The device according to claim 10, wherein the first contacts and the second contacts are formed along a single line or double lines.