Gate-all-around type of semiconductor device and method of fabricating the same

• US 20070200178A1
• Filed: 04/10/2007
• Published: 08/30/2007
• Est. Priority Date: 06/08/2004
• Status: Abandoned Application

• Current Assignee: Eun-Jung Yun, Sung-Min Kim, Sung-Young Lee
• Original Assignee: Eun-Jung Yun, Sung-Min Kim, Sung-Young Lee
• Inventors: Lee, Sung-young, Kim, Sung-min, Yun, Eun-jung
• Application Number:
  US11/783,518
• Publication Number:
  US 20070200178A1
• Time in Patent Office: Days
• US Class Current: 257/353
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

Claims

1. A gate-all-around (GAA) transistor, comprising:

a first pillar comprising a source region;

a second pillar comprising a drain region and spaced from the first pillar;

a channel region bridging the source region of said first pillar and the drain region of said second pillar;

a gate insulating layer and a gate electrode which surround the channel region; and

insulative material disposed between the pillars laterally of said gate electrode below said channel region.

2. The GAA transistor of claim 1, further comprising mask patterns disposed on said pillars, respectively, and insulative material disposed between the mask patterns and laterally of said gate electrode above said channel region.

3. The GAA transistor of claim 1, further comprising a counter-doped region located below said gate electrode.

4. The GAA transistor of claim 1, wherein said channel region is an Si epitaxial layer.

5. The GAA transistor of claim 1, wherein said channel region has an upper surface that is disposed at the same level as the upper surfaces of said pillars.

6. The GAA transistor of claim 1, wherein said channel region has an upper surface that is disposed at a level above the upper surfaces of said pillars.

7. The GAA transistor of claim 1, wherein said channel region has an upper surface that is disposed at a level beneath the upper surfaces of said pillars.

8. The GAA transistor of claim 1, wherein the channel region overlaps the source and drain regions completely at respective ends of the channel region.

9. The GAA transistor of claim 1, comprising a mono-crystalline substrate that comprises said pillars.

10. A gate-all-around (GAA) transistor, comprising:

a first pillar comprising a source region;

a second pillar comprising a drain region and spaced from the first pillar;

a channel region bridging the source region of said first pillar and the drain region of said second pillar; and

a gate insulating layer and a gate electrode which surround the channel region, the gate electrode having a lower portion disposed below the channel region, and the width of the channel region from the source region of said first pillar to the drain region of said second pillar being greater than the width of the lower portion of the gate electrode as measured in the same direction from the source region of said first pillar to the drain region of said second pillar.

11. The GAA transistor of claim 10, and further comprising mask patterns disposed on said pillars, respectively, and insulative material disposed between the mask patterns and laterally of said gate electrode above said channel region.

12. The GAA transistor of claim 10, further comprising a counter-doped region located below said gate electrode.

13. The GAA transistor of claim 10 ;

, wherein said channel region is an Si epitaxial layer.

14. The GAA transistor of claim 10, wherein said channel region has an upper surface that is disposed at the same level as the upper surfaces of said pillars.

15. The GAA transistor of claim 10, wherein said channel region has an upper surface that is disposed at a level above the upper surfaces of said pillars.

16. The GAA transistor of claim 10, wherein said channel region has an upper surface that is disposed at a level beneath the upper surfaces of said pillars.

17. The GAA transistor of claim 10, wherein the channel region overlaps the source and drain regions completely at respective ends of the channel region.

18. The GAA transistor of claim 10, comprising a mono-crystalline substrate that comprises said pillars.