Double density NROM with nitride strips (DDNS)

• US 20070200180A1
• Filed: 12/28/2006
• Published: 08/30/2007
• Est. Priority Date: 02/28/2006
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Irani, Rustom, Shappir, Assaf, Bloom, Ilan
• Granted Patent: US 7,638,835 B2
• Time in Patent Office: Days
• US Class Current: 257/374
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Claims

1. A method of making a non-volatile memory (NVM) cell comprising:

providing an ONO layer comprising a bottom layer of oxide (O), a layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate;

processing the ONO layer to create a number (n) of individual ONO stacks;

processing the ONO stacks so as to separate at least the nitride layers of the stacks into two distinct portions; and

forming a given memory cell from a portion of one stack and a portion of an adjacent (neighboring) stack.

2. The method of claim 1, wherein the NVM cell is an NROM cell.

3. The method of claim 1, wherein:

when separating the ONO stacks, leaving the bottom layer of oxide in place.

4. The method of claim 1, further comprising:

using a nitride mask having openings and an etch process to create the individual ONO stacks.

5. The method of claim 4, further comprising:

depositing a layer of oxide in the openings of the nitride mask, thereby reducing the size of the openings.

6. The method of claim 5, further comprising:

filling the openings with poly.

7. The method of claim 6, further comprising:

removing remnants of the nitride mask, leaving poly structures having their sidewalls covered by the oxide which was deposited in the openings of the nitride mask.

8. The method of claim 7, further comprising:

stripping the oxide from the sidewalls of the poly structures.

9. The method of claim 8, further comprising:

depositing and processing a poly liner to form poly sidewalls on the poly structures.

10. The method of claim 9, further comprising:

removing exposed portions of the ONO layer between adjacent poly structures.

11. The method of claim 10, further comprising:

implanting bitline diffusions.

12. The method of claim 1, further comprising:

prior to processing the ONO layer to create the individual ONO stacks, depositing at least one sacrificial layer atop the ONO layer.

13. The method of claim 12, wherein the at least one sacrificial layer comprises:

a layer of poly.

14. The method of claim 12, wherein the at least one sacrificial layer comprises:

a layer of sacrificial poly followed by a layer of sacrificial oxide.

15. The method of claim 12, further comprising:

in a subsequent processing step, removing substantially all of the layer of sacrificial oxide.

16. The method of claim 15, further comprising:

in a subsequent processing step, removing all but a portion of the layer of sacrificial poly.

17. A method of making a non-volatile memory (NVM) cell comprising:

providing an ONO layer comprising a bottom layer of oxide (O), an layer of nitride (N) and a top layer of oxide (O) on a semiconductor substrate;

depositing sacrificial layers of material on the ONO layer;

processing the ONO layer and sacrificial layers to create a number (n) of individual ONO stacks covered by sacrificial layers;

processing the ONO stacks so as to separate each ONO stack into two portions; and

forming a given memory cell from a portion of one ONO stack and a portion of an adjacent (neighboring) ONO stack.

18. The method of claim 17, wherein the NVM cell is an NROM cell.

19. Non-volatile memory (NVM) cell comprising:

an ONO layer disposed on a semiconductor substrate and comprising a plurality (n) of ONO stacks; and

for a given memory cell, a gate formed atop a portion of a given ONO stack and an adjacent portion of another ONO stack.

20. The NVM cell of claim 19, further comprising:

vestiges of a sacrificial poly layer on outer edges of the ONO stacks.

21. The NVM cell of claim 19, wherein:

the NVM cell is an NROM cell.