Trigger architecture, measurement system and method of use

• US 20070200550A1
• Filed: 02/28/2006
• Published: 08/30/2007
• Est. Priority Date: 02/28/2006
• Status: Abandoned Application

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Corredoura, Paul
• Application Number:
  US11/363,939
• Publication Number:
  US 20070200550A1
• Time in Patent Office: Days
• US Class Current: 324/121.R
• CPC Class Codes: G01R 13/0254 for triggering, synchronisation

Abstract

A trigger architecture for generating a trigger; a measurement system including a trigger architecture; and a method of processing measurement data are described.

Claims

1. A trigger architecture, comprising:

a plurality of parallel analog-to-digital converters (ADCs) operative to garner data samples in parallel from an input signal at different times in a clock signal period; and

a logic block comprising a plurality of digital comparators, which are adapted to compare each of the data samples to one or more threshold values in parallel.

2. The trigger architecture of claim 1, wherein the logic block further comprises a field programmable gate array (FPGA).

3. The trigger architecture of claim 2, wherein the logic block is part of an application specific integrated circuit (ASIC).

4. The trigger architecture of claim 1, wherein each of the plurality of ADCs includes a sequence of N (N=integer) ADCs and, excepting a first ADC, each ADC has a respective clocking signal that is delayed compared to the respective clocking signals of previous ADCs of the sequence of ADCs.

5. The trigger architecture of claim 1, further comprising a threshold block connected to each of the plurality of ADCs and operative to receive each of the data samples in parallel.

6. The trigger architecture of claim 5, wherein the threshold block is adapted to calculate one or more of a maximum value of the data samples, a minimum value of the data samples, and an average value of the data samples.

7. The trigger architecture of claim 1, further comprising a decimation block operative to receive the data samples from the plurality of ADCs and to provide a lower sample rate representation of the input signal to the plurality of digital comparators of the logic block.

8. The trigger architecture of claim 1, further comprising a resampler and decimator block operative to receive the data samples from the plurality of ADCs and to provide the data samples to the plurality of digital comparators of the logic block.

9. A measurement system, comprising:

a trigger architecture having;

a plurality of analog-to-digital converters (ADCs) operative to garner data samples in parallel from an input signal at different times in a clock signal period; and

a logic block comprising a plurality of digital comparators, which are adapted to compare each of the data samples to one or more threshold values.

10. The measurement system of claim 9, further comprising an oscilloscope.

11. The measurement system of claim 9, wherein the logic block is a field programmable gate array (FPGA).

12. The measurement system of claim 9, wherein the logic block is part of an application specific integrated circuit (ASIC).

13. The measurement system of claim 9, wherein each of the plurality of ADCs includes a sequence of N (N=integer) ADCs and, excepting a first ADC, each ADC has a respective clocking signal that is delayed compared to the respective clocking signals of previous ADCs of the sequence of ADCs.

14. The measurement system of claim 9, wherein the trigger architecture further comprises:

a threshold block connected to each of the plurality of ADCs and operative to receive each of the data samples in parallel.

15. The measurement system of claim 9, wherein the trigger architecture further comprises:

a decimation block operative to receive the data samples from the plurality of ADCs and to provide a lower sample rate data stream to the plurality of digital comparators of the logic block.

16. The measurement system of claim 9, wherein the trigger architecture further comprises:

a resampler and decimator block operative to receive the data samples from the plurality of ADCs and to provide data samples to the plurality of digital comparators of the logic block.

17. In a measurement system, a method of processing measurement data, the method comprising:

receiving an analog input signal;

sampling the analog input signal in parallel, wherein the sampling is sequential in time;

converting the samples to digital data;

comparing the data to one or more thresholds in parallel; and

if a threshold is met, generating a trigger to a display of a waveform based on the digital data.

18. The method of claim 17, further comprising, before the comparing, decimating the digital data.

19. The method of claim 17, further comprising, before the comparing, resampling and decimating the digital data.

20. The method of claim 17, further comprising identifying a runt pulse by comparing one of the data to an average value.