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Trigger architecture, measurement system and method of use

  • US 20070200550A1
  • Filed: 02/28/2006
  • Published: 08/30/2007
  • Est. Priority Date: 02/28/2006
  • Status: Abandoned Application
First Claim
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1. A trigger architecture, comprising:

  • a plurality of parallel analog-to-digital converters (ADCs) operative to garner data samples in parallel from an input signal at different times in a clock signal period; and

    a logic block comprising a plurality of digital comparators, which are adapted to compare each of the data samples to one or more threshold values in parallel.

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