Versatile semiconductor test structure array
First Claim
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1. A semiconductor test structure array comprising:
- a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; and
an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.
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Abstract
This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUTs) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.
27 Citations
20 Claims
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1. A semiconductor test structure array comprising:
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a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; and an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs, wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor test structure array comprising:
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a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; and an access-control circuitry within the each unit cell for controlling accesses to the one or more DUTs, wherein the access-control circuitries are isomorphic and the each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and wherein at least one of the CTGs further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A semiconductor test structure array comprising:
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a row decoder; a column decoder; a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; and an access-control circuitry within the each unit cell for controlling accesses to the one or more DUTs, wherein the access-control circuitries are isomorphic and the each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and wherein the CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test. - View Dependent Claims (20)
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Specification