Read only memory device with bitline leakage reduction
First Claim
1. A Read Only Memory (ROM) device containing a plurality of memory cells accessed through a plurality of wordlines and a plurality of bitlines, each of the memory cells comprises:
- a first main terminal of a controlled switch connected to one of the plurality of bitlines of the memory cell, wherein a control terminal of the controlled switch is connected to one of the plurality of wordlines of the memory cell; and
a second main terminal of the controlled switch connected to the complement of the wordline if the memory cell stores a “
0”
, the second main terminal being left unconnected if the memory cell stores a “
1”
.
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Accused Products
Abstract
A memory chip configuration aims that reduces the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of—a n×m FET matrix, vertically running bitlines—each shared by a column in the array, horizontally running wordlines—each shared by a row in the array, horizontally running sourcelines—each shared by a row in the array. The sourceline signal for a row is generated by complementing the wordline signal for the same row. The memory cell read operations with the proposed configuration, substantially control the bitline leakage current thereby enhancing the memory speed by reducing the noise during read operations. Also the configuration is unconstrained by design parameters that include size and geometries of memory chips, cell densities, complexity of memory structures, fabrication technologies, etc.
55 Citations
20 Claims
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1. A Read Only Memory (ROM) device containing a plurality of memory cells accessed through a plurality of wordlines and a plurality of bitlines, each of the memory cells comprises:
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a first main terminal of a controlled switch connected to one of the plurality of bitlines of the memory cell, wherein a control terminal of the controlled switch is connected to one of the plurality of wordlines of the memory cell; and
a second main terminal of the controlled switch connected to the complement of the wordline if the memory cell stores a “
0”
, the second main terminal being left unconnected if the memory cell stores a “
1”
. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A Read Only Memory (ROM) device comprising:
a plurality of memory cells accessed through a plurality of wordlines and a plurality of bitlines, the memory cell having a controlled switch, wherein the controlled switch comprises;
a first main terminal of the controlled switch connected to one of the plurality of bitlines of the memory cell, wherein a control terminal of the controlled switch is connected to one of the plurality of wordlines of the memory cell; and
a second main terminal of the controlled switch connected to the complement of the wordline if the memory cell stores a “
0”
, the second main terminal being left unconnected if the memory cell stores a “
1”
.- View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for creating an improved Read Only Memory (ROM) device, the method comprising:
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providing a controlled switch;
connecting a first main terminal of the controlled switch to the bitline of the memory cell;
connecting the control terminal of the controlled switch to the wordline of the memory cell; and
connecting the second main terminal of the controlled switch to the complement of the wordline if the memory cell stores a “
0”
, and leaving the second main terminal unconnected if the memory cell stores a “
1”
. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification
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- Resources
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Current AssigneeSTMicroelectronics Pvt Ltd. (STMicroelectronics NV)
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Original AssigneeSTMicroelectronics Pvt Ltd. (STMicroelectronics NV)
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InventorsChatterjee, Kallol, Asthana, Vivek, Dasani, Jitendra
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Application NumberUS11/648,155Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current365/185.50CPC Class CodesG11C 17/10 in which contents are deter...
