PMA RX in course loop for high speed sampling
First Claim
1. A high data rate transceiver, comprising:
- a first programmable receive PMA module coupled to produce a first serial data;
a first clock and data recovery (CDR) coupled to receive the first serial data, the first CDR producing a first recovered clock in a first CDR receive mode of operation and producing a first sample clock in a first CDR sample mode of operation;
a second programmable receive PMA module coupled to produce a second serial data;
a second CDR coupled to receive the second serial data, the second CDR producing a second recovered clock in the first CDR receive mode of operation and producing a second sample clock in a second CDR sample mode of operation;
the first and second CDRs each further including selectable fine loop and coarse loop PLLs; and
programmable logic fabric further comprising;
mode determination logic for determining, for each of the first and second CDRs, the CDR receive mode of operation; and
mode switching logic for generating and providing mode switching signals to the first and second CDRs to select which of the selectable fine loop PLL and course loop PLL are selectively coupled within each CDR to provide a corresponding receive or sample clock.
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Accused Products
Abstract
A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
32 Citations
20 Claims
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1. A high data rate transceiver, comprising:
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a first programmable receive PMA module coupled to produce a first serial data;
a first clock and data recovery (CDR) coupled to receive the first serial data, the first CDR producing a first recovered clock in a first CDR receive mode of operation and producing a first sample clock in a first CDR sample mode of operation;
a second programmable receive PMA module coupled to produce a second serial data;
a second CDR coupled to receive the second serial data, the second CDR producing a second recovered clock in the first CDR receive mode of operation and producing a second sample clock in a second CDR sample mode of operation;
the first and second CDRs each further including selectable fine loop and coarse loop PLLs; and
programmable logic fabric further comprising;
mode determination logic for determining, for each of the first and second CDRs, the CDR receive mode of operation; and
mode switching logic for generating and providing mode switching signals to the first and second CDRs to select which of the selectable fine loop PLL and course loop PLL are selectively coupled within each CDR to provide a corresponding receive or sample clock. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A transceiver for processing high data rate serial data, comprising:
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transceiver circuitry for transmitting and receiving the high data rate serial data;
phase-locked loop circuitry further including a selectable coarse loop PLL and a selectable fine loop PLL, wherein;
the selectable coarse loop PLL for producing a coarse error signal reflecting a difference between a reference signal and a coarse loop feedback signal; and
the selectable fine loop PLL for producing a fine loop error adjustment signal based upon a difference in a recovered clock and the high data rate serial data;
a loop filter for producing an error signal based on at least one of the fine loop error adjustment signal from a fine loop charge pump and the coarse error signal from a coarse loop charge pump;
a controlled oscillation module for producing a receiver clock in the form of an oscillating signal based on the error signal produced by the loop filter;
a divider for dividing the oscillating signal to produce the recovered clock to a phase detector;
a selectable coarse loop selection switch coupled between the coarse loop charge pump and the loop filter;
coarse loop logic circuitry for providing control commands to couple the selectable coarse loop PLL to the loop filter based upon one of a sample mode signal or a detected difference between a reference clock and the coarse loop feedback signal;
a selectable fine loop selection switch coupled between the fine loop charge pump and the loop filter; and
mode determination logic external to the fine loop PLL and coarse loop PLL coupled to produce mode switching signals to selectively switch the selectable coarse loop PLL and selectable fine loop PLL into and out of coupling according to defined operational logic within the mode determination logic. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification