Wafer level package for very small footprint and low profile white LED devices

• US 20070202623A1
• Filed: 10/27/2006
• Published: 08/30/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Current Lighting Solutions, LLC (f/k/a GE Lighting Solutions, LLC) (American Industrial Partners)
• Original Assignee: Gelcore (General Electric Company)
• Inventors: Gao, Xiang, Sackrison, Michael
• Granted Patent: US 7,718,449 B2
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil

Abstract

A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

Claims

1. A method for fabricating a light emitting diode package, the method comprising:

forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing;

forming electrical vias in a sub mount, the electrical vias passing from a front-side of the sub-mount to a back-side of the sub-mount;

flip chip bonding the light emitting diode chips on the front-side of the sub-mount such that each light emitting diode chip electrically contacts selected electrical vias;

thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and

after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

2. The method as set forth in claim 1, further comprising:

after the disposing of the phosphor, separating the submount to form surface mount light emitting diode packages.

3. The method as set forth in claim 1, further comprising:

disposing an underfill material between the front-side of the sub-mount and the light emitting diode chips.

4. The method as set forth in claim 3, wherein the underfill material is disposed before flip-chip bonding.

5. The method as set forth in claim 3, wherein the underfill material is disposed after the flip-chip bonding.

6. The method as set forth in any one of claims 1, wherein the thinning or removing comprises removing the substrate.

7. The method as set forth in claim 6, wherein the removing comprises removing the substrate by an optical lift-off process.

8. The method as set forth in claim 6, wherein the removing comprises removing the substrate by a laser lift-off process.

9. The method as set forth in any one of claims 8, wherein the light emitting diode chips are group III nitride-based light emitting diode chips.

10. The method as set forth in claim 9, wherein the light emitting diode chips emit UV light and the disposing of a phosphor comprises disposing a phosphor that produces substantially white converted light.

11. The method as set forth in claim 9, wherein the light emitting diode chips emit violet or blue light and the disposing of a phosphor comprises disposing a phosphor that produces substantially yellowish converted light that blends with the violet or blue light to output substantially white light.

12. The method as set forth in claim 1, wherein the disposing of a phosphor comprises disposing a phosphor over substantially the entire frontside of the submount including the light emitting diode chips.

13. The method as set forth in claim 1, wherein the disposing of a phosphor comprises disposing a phosphor over the light emitting diode chips without substantial disposing onto exposed areas of the frontside of the submount.

14. The method as set forth in claim 13, wherein the disposing of a phosphor comprises disposing the phosphor over each light emitting diode chip in an area including the light emitting diode chip that is less than 20 microns larger than the light emitting diode chip.

15. A surface mount LED package having a tight footprint and small vertical image size fabricated by a method comprising:

forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing;

forming electrical vias in a sub mount, the electrical vias passing from a front-side of the sub-mount to a back-side of the sub-mount;

flip chip bonding the light emitting diode chips on the front-side of the sub-mount such that each light emitting diode chip electrically contacts selected electrical vias;

thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and

after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

16. The LED package as set forth in claim 15, wherein the light emitting diode chips after thinning or removal of the substrate have thicknesses of less than 5 microns.

17. The light emitting diode package as set forth in claim 15, wherein the phosphor is deposited over the entire frontside of the submount.

18. The light emitting diode package as set forth in claim 15, wherein the phosphor is selectively deposited in areas each encompassing and slightly larger than one of the light emitting diode chips.

19. The light emitting diode package as set forth in claim 18, wherein the areas of selective phosphor deposition each extend less than 20 microns larger than the light emitting diode chip.