Manufacturing process for integrated piezo elements

• US 20070202628A1
• Filed: 02/26/2007
• Published: 08/30/2007
• Est. Priority Date: 02/24/2006
• Status: Abandoned Application

• Current Assignee: Telefunken Semiconductors GmbH & Co. KG.
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Wuertz, Alida
• Application Number:
  US11/710,551
• Publication Number:
  US 20070202628A1
• Time in Patent Office: Days
• US Class Current: 438/53
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0054 integral with a semiconducting diaphragm

Abstract

A method is provided for the production of integrated microelectromechanical elements, in which first a silicon layer is formed on an insulation layer, then a piezoresistive layer on or in the silicon layer, and then at least one etch opening for etching at least one cavity substantially within the silicon layer. The shape of the cavity in the silicon layer is predefined by arrangement of additional vertical and horizontal etch stop layers, and the etching process is readily reproducible. The method is suitable for being integrated into standard fabrication processes particularly with circuit components needed for signal conditioning and signal processing.

Claims

1. A method for producing integrated microelectromechanical elements, the method comprising:

forming a silicon layer on an insulation layer;

forming a piezoresistive layer on or in the silicon layer; and

forming at least one etch opening for etching at least one cavity substantially within the silicon layer.

3. The method according to claim 1, further comprising the step of forming a trench for laterally limiting the cavity.

4. The method according to claim 3, wherein a circumferential trench is created.

5. The method according to claim 1, wherein, to form the piezoresistive layer, the silicon layer is doped or implanted at least in subregions.

6. The method according to claim 1, wherein a doped or implanted polysilicon is provided as a starting material for the piezoresistive layer.

7. The method according to claim 1, wherein a diffusion-doped polysilicon is provided as a starting material for the piezoresistive layer, at least in subregions.

8. The method according to claim 1, further comprising the step of forming a second insulation layer on the silicon layer before the formation of the piezoresistive layer.

9. The method according to claim 1, further comprising the step of forming piezoresistors by patterning the piezoresistive layer.

10. The method according to claim 1, further comprising the step of forming piezoresistors by selective doping of the silicon layer, wherein the silicon layer is polysilicon.

11. The method according to claim 1, wherein the at least one etch opening is sealed.

12. The method according to claim 1, wherein the electrical contacting of the piezoresistive layer is provided before the formation of a cavity.

13. The method according to claim 1, wherein a protective layer of Si₃N₄, is provided to protect the piezoresistive layer.

14. The method according to claim 1, wherein, during the sealing of the etch openings, a defined internal pressure is produced in the cavities.

15. The method according to claim 1, wherein the insulation layer is formed on a supporting layer.

16. The method according to claim 9, wherein four piezoresistors are connected to form a Wheatstone bridge.

18. The Microelectromechanical element according to claim 13, wherein a second insulation layer is disposed as a self-supporting membrane below the patterned piezoresistive layer.

2. A method for producing integrated microelectromechanical elements, the method comprising:

first, forming a silicon layer on an insulation layer;

second, forming at least one etch opening for etching at least one cavity substantially within the silicon layer; and

third, forming a piezoresistive layer on or in the silicon layer,

wherein the first, second and third steps are performed sequentially.

17. A Microelectromechanical element comprising:

an insulation layer;

a silicon layer; and

a patterned piezoresistive layer,

wherein, within the silicon layer, a cavity and above the cavity a self-supporting membrane are provided, on which are disposed at least parts of the piezoresistive, patterned layer.