METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE
First Claim
1. A method of manufacturing a semiconductor device comprising the steps of:
- (a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;
(b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region and forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively;
(c) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes;
(d) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode;
(e) forming a second offset sidewall with a silicon oxide film on said first offset sidewall;
(f) ion implanting said P-type impurity into said first PMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.
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Accused Products
Abstract
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
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Citations
2 Claims
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1. A method of manufacturing a semiconductor device comprising the steps of:
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(a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;
(b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region and forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively;
(c) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes;
(d) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode;
(e) forming a second offset sidewall with a silicon oxide film on said first offset sidewall;
(f) ion implanting said P-type impurity into said first PMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.
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2. A method of manufacturing a semiconductor device comprising the steps of:
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(a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a second NMOS region for forming a second NMOS transistor with a higher operating voltage than said first NMOS transistor;
(b) selectively forming a first gate insulating film in both said first NMOS region and said second NMOS region;
(c) selectively forming a first gate insulating film greater in thickness than said first gate insulating film on said second NMOS region;
(d) forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and on said second gate insulating film of said second NMOS region, respectively;
(e) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes;
(d) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode;
(e) forming a second offset sidewall with a silicon oxide film on said first offset sidewall;
(f) ion implanting said N-type impurity into said second NMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.
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Specification