Low voltage power MOSFET device and process for its manufacture

• US 20070202650A1
• Filed: 04/27/2007
• Published: 08/30/2007
• Est. Priority Date: 04/04/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thapar, Naresh
• Granted Patent: US 8,487,368 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low R_DSON and increased V_DSMAX and V_GSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000Å to 1400Å and the nitride is subsequently removed and a thin oxide, for example 320Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon. A very lightly doped diffusion of 1000Å to 2000Å in depth could also be formed around the bottom of the trench and is depleted at all times by the inherent junction voltage to further reduce Miller capacitance and switching loss.

Claims

1. The process for forming a trench type MOSgated device;

said process comprising the steps of etching a trench having spaced side walls and a bottom surface into a silicon wafer wherein said bottom surface and side walls meet at a sharp angle;

forming a silicon nitride layer on said side walls and said bottom surface;

removing said silicon nitride layer from said bottom surface only;

forming silicon dioxide layer on said trench bottom which has a thickness in excess of 1000Å

on said bottom surface and rounding said bottom surface and sharp corners while forming said bottom silicon dioxide layer, and thereafter removing the silicon nitride layer on said walls and then forming silicon dioxide layers on said side walls which have a thickness substantially less than 1000Å

.

2. The process of claim 1 wherein said silicon dioxide layers on said walls have a thickness of about 320Å

.

3. A method for manufacturing a semiconductor device comprising:

providing a substrate of a first conductivity;

forming an epitaxial semiconductor layer of said first conductivity over said substrate, said epitaxial layer having a first concentration of dopants of said first conductivity;

forming a region of said first conductivity in said epitaxial layer, said region of said first conductivity having a concentration of dopants selected so that said region is depleted by the inherent junction voltage between said region and its surrounding region;

forming a channel region of said second conductivity in said epitaxial layer;

forming vertical trenches in said epitaxial layer, said trenches terminating at said region of said first conductivity; and

forming a gate structure in each of said trenches.

4. A method according to claim 3, wherein said region of said first conductivity is about three microns deep.

5. A method according to claim 3, wherein said region of said first conductivity has a dopant concentration of about 1×

10¹⁴ atoms/cm³.

6. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

epitaxially forming a semiconductor layer of first conductivity on said substrate;

forming a channel region in said epitaxially formed semiconductor layer through implantation of dopants of second conductivity type, said implantation introducing defects in said epitaxially formed semiconductor layer;

forming trenches in said epitaxially formed layer, said trenches extending through said channel region;

forming source regions in said channel region adjacent said trenches, said source regions extending to a depth below said defects in said epitaxially formed layer.

7. A method according to claim 6, further comprising forming an oxide layer on said sidewalls of said trenches and said bottom of said trenches, wherein the oxide layer at the bottom of said trenches is thicker than said oxide at said sidewalls of said trenches.

8. A method according to claim 7, wherein said thick oxide at the bottom of said trenches is formed by first covering said sidewall of said trenches with an oxidation retardant and then oxidizing said bottom of said trenches to a desired thickness.

9. A method according to claim 7, wherein said oxidation retardant is a nitride.

10. A method according to claim 7, wherein said thick oxide at the bottom of said trenches is formed by first amorphizing the semiconductor material at said bottom of said trenches and then oxidizing said bottom of said trenches and said sidewalls of said trenches at the same time.

11. A method according to claim 7, wherein said oxide at said bottom of said trenches is 1000-1400 angstroms.

12. A method according to claim 7, wherein said oxide at said sidewalls of said trenches is about 300-320 angstroms thick.

13. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor layer of first conductivity;

forming at least a pair of body regions of second conductivity in said semiconductor layer, said body regions being spaced from one another by a common conduction region;

forming a gate structure which extends over at least said common conduction region between said body regions;

forming self-depleting region of one of said first conductivity and said second conductivity below said gate structure in said common conduction region, said self-depleting region being doped such that it depletes automatically due to a voltage junction with its surrounding region.

14. A method according to claim 13, further comprising source regions in said body regions, each source region being spaced from said common conduction region by an invertible channel.