Method For Producing Mixed Stacked Structures, Different Insulating Areas And/Or Localised Vertical Electrical conducting Areas

• US 20070202660A1
• Filed: 10/06/2005
• Published: 08/30/2007
• Est. Priority Date: 10/06/2004
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Moriceau, Hubert, Morales, Christophe, Fournel, Frank
• Granted Patent: US 7,781,300 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

The invention relates to a method for producing a semiconducting structure including:

controlled formation, through a mask (31), in a first substrate (30) in a semiconducting material, of at least one first area in an insulating material (36), up to the level of the lower surface (35) of the mask, before or during the removal of the mask.

Claims

1-56. -56. (canceled)

57. A method for producing a semiconducting structure, including:

controlled information through a mask, in a first substrate in a semiconducting material, of at least one first area in an insulating material, up to the level of the lower surface of the mask, before removal of the mask, so that after removal of the mask the upper level of this first area is at the level of the lower surface of the mask.

58. The method according to claim 57, the formation of insulating material including a step for controlled growth of said insulating material up to the level of the lower surface of the mask, and then removal of the mask.

59. The method according to claim 57, the insulator formation step including:

a1) a substep for controlled growth of an insulating material, up to above the level of the lower surface of the mask, and

a2) a substep for selectively thinning the insulating material, in order to bring it back to the level of the lower surface of the mask.

60. The method according to claim 57, the insulator formation including:

a1) a substep for controlled growth of an insulating material, up to above the level of the lower surface of the mask, and

a2) a substep for selectively thinning the insulating material, in order to bring it back to a level higher than the lower surface of the mask, thereby maintaining a residual insulator layer above this surface.

61. The method according to claim 60, the residual layer being at least partly removed during removal of the mask.

62. The method according to claim 60, the residual layer being at least partly removed during removal of a superficial layer formed on the mask during the substep a1).

63. The method according to claim 59, the step a2 being performed by chemical etching.

64. The method according to claim 59, the substep a1) being a step for controlled growth of an insulating material above the upper surface of the mask.

65. The method according to claim 64, the removal of at least one portion of the insulating material at the base of the mask leaving at least one overlapping area.

66. The method according to claim 64, the removal of at least one portion of the insulating material at the base of the mask being uniform, at least one portion of the mask being used as stopping areas during this removal.

67. The method according to claim 64, the substep a1) including a substep for growing overlapping areas above the upper surface of the mask.

68. The method according to claim 65, further including removal of the overlapping areas.

69. The method according to claim 57, the substrate further including an insulating layer at the surface.

70. The method according to claim 69, further including a step for suppressing the insulator layer in order to form an alternation of semiconducting areas and of insulating areas.

71. The method according to claim 69, the insulating layer having a thickness between 1 nm and 0.5 μ

m.

72. The method according to claim 57, the substrate further including a conducting layer at the surface.

73. The method according to claim 72, the conducting layer being in suicide or in metal or in doped Si.

74. The method according to claim 72, the conducting layer being covered with a protective layer.

75. The method according to claim 74, the protective layer not being removed after removal of the mask.

76. The method according to claim 57, including etching of the first substrate in a semiconducting material, through the mask, forming at least one etched area in the semiconducting material, and optionally in the insulating surface layer or optionally in the conducting layer and optionally in its protective layer, the insulating material being formed in at least this etched area.

77. The method according to claim 76, the etched area having a depth in the first semiconducting material between 1 nm and 10 μ

m.

78. The method according to claim 57, the removal of the mask being performed selectively relatively to the insulating material.

79. The method according to claim 57, the semiconducting material being silicon or Si₁₋

xGe_x (0≦

x≦

1)

80. The method according to claim 57, the insulating material being selected from the group consisting of SiO₂, Al₂O₃, AlN, SiON, Si₃N₄, diamond, HfO₂, and a dielectric material with a high dielectric constant.

81. The method according to claim 57, the mask being in nitride Si₃N₄, or Al₂O₃ or AlN.

82. The method according to claim 57, further including an assembly step with a second substrate.

83. The method according to claim 82, the assembly being achieved by molecular adhesion.

84. The method according to claim 82, the second substrate being in a second semiconducting material.

85. The method according to claim 84, the second substrate further including an insulator layer on the second semiconducting material.

86. The method according to claim 84, the first substrate having at least one area of a first conductivity type, and the second substrate having at least one area of opposite conductivity type.

87. The method according to claim 82, further including a step for thinning the first and/or the second substrate.

88. The method according to claim 87, the step for thinning either one or both of the substrates being performed by forming an embrittlement layer or area.

89. The method according to claim 88, the embrittlement layer or area being produced by a porous silicon layer.

90. The method according to claim 89, the formation of an embrittlement layer or area being achieved by implanting ions in the first or second substrate.

91. The method according to claim 90, the implanted ions being hydrogen ions, or a mixture of hydrogen ions and helium ions.

92. The method according to claim 91, the thinning step being obtained by polishing or etching.

93. The method according to claim 82, the first and/or second substrate including at least one first conductivity area and a second conductivity area at the surface.

94. The method according to claim 84, the second substrate including at least one surface circuit or component portion.

95. The method according to claim 57, the material of the first substrate including areas with different dopings.

96. The method according to claim 57, the formation of insulator through the mask at least partly including thermal oxidation of the semiconducting substrate.

97. The method according to claim 96, further including deposition of insulator or oxide.

98. A method for producing a semiconducting structure including the formation:

a) of a first insulating area in a semiconducting substrate, and

b) then the formation of at least a second insulating area in the same substrate, the steps a) and b) being carried out according to claim 57.

99. The method according to claim 98, the steps a) and b) being carried out with different masks.

100. The method according to claim 98, at least two of the formed insulating areas having different depths and/or widths in the substrate and/or being formed with different insulating materials.

101. The method according to claim 57, an insulating film being produced on at least one of the two substrates.

102. A method for producing a semiconducting component, including:

formation or controlled growth of an insulator through a mask, in a first area of a semiconducting substrate, and up to above the level of the lower surface of a mask covering at least a second area of the substrate, or covering an insulating layer or a conducting layer or a protective layer of a conducting layer covering at least a second area of the substrate, and

etching of the insulator, selectively relatively to the mask, and etching of the mask, selectively relatively to the insulator, in order to bring the other surface of the insulator back to the level defined by the lower surface of the mask.

103. The method according to claim 102, etching of the insulator leaving a residual insulator layer above the level defined by the lower surface of the mask.

104. The method according to claim 103, the residual layer being at least partly removed during etching of a superficial layer covering the mask and/or at least partly removed during ache etching of the mask.

105. The method according to claim 102, including etching of the first area of the substrate.

106. The method according to claim 105, the etched area having a depth in the substrate between 1 nm and 10 μ

m.

107. The method according to claim 102, the semiconducting material being silicon or Si₁₋

xGe_x (0≦

x≦

1).

108. The method according to claim 102, the insulating material being selected from the group consisting of Si₂, Al₂O₃, AlN, SiON, Si₃N₄, diamond, HfO₂, and a dielectric material with a high dielectric constant.

109. The method according to claim 102, the mask being in nitride Si₃N₄, or Al₂O₃ or AlN.

110. The method according to claim 102, further including an assembly step with a second substrate.

111. The method according to claim 110, the assembly being achieved by molecular adhesion.

112. The method according to claim 110, the second substrate being in a second semiconducting material.

113. The method according to claim 112, the second substrate further including an insulator layer on the second semiconducting material.

114. The method according o claim 112, the first substrate having at least one area of a first conductivity type, and the second substrate having at least one area of opposite conductivity type.

115. The method according to claim 110, further including a step for thinning the first and/or the second substrate.

116. The method according to claim 115, the step for thinning either one or both of the substrates being performed by forming an embrittlement layer or area.

117. The method according to claim 116, the embrittlement layer or area being produced by a porous silicon layer.

118. The method according to claim 117, the formation of an embrittlement layer or area being achieved by implanting ions in the first or second substrate.

119. The method according to claim 118, the implanted ions being hydrogen ions, or a mixture of hydrogen ions and helium ions.

120. The method according to claim 119, the thinning step being obtained by polishing or etching.

121. The method according to claim 110, the first and/or second substrate including at least one first conductivity area and a second conductivity area at the surface.

122. The method according to claim 112, the second substrate including at least one surface circuit or component portion.

123. The method according to claim 102, the material of the first substrate including areas with different dopings,

124. The method according to claim 102 the formation of insulator through the mask at least partly including thermal oxidation of the semiconducting substrate.

125. The method according to claim 124, further including deposition of insulator or oxide.

126. A method for producing a semiconducting structure including the formation:

a) of a first insulating area in a semiconducting substrate, and

b) then the formation of at least a second insulating area in the same substrate, the steps a) and b) being carried out according to claim 102.

127. The method according to claim 126, the steps a) and b) being carried out with different masks.

128. The method according to claim 126, at least two of the formed insulating areas having different depths and/or widths in the substrate and/or being formed with different insulating materials.

129. The method according to claim 102, an insulating film being produced on at least one of the two substrates.

130. A semiconducting device, including a semiconducting substrate, at least one insulating area in this substrate, a surface of this insulating area being flush with the surface of the semiconducting material with an accuracy less than ±

5 nm.

134. The device according to claim 130, the semiconducting material being silicon or Si₁₋

xGe_x (0≦

x≦

1).

136. The device according to claim 130, the insulating material of the insulating area being selected from the group consisting of in SiO₂, Al₂O₃, AlN, SiON, Si₃N₄, diamond, HfO₂, and a dielectric material with high dielectric constant.

131. A semiconducting device, including a semiconducting substrate, at least one insulating area in this substrate, a conducting layer on this substrate, outside the insulating areas, this conducting layer being possibly covered with a protective layer, a surface of the insulating area being flush with the surface of the conducting layer or possibly that of the protective layer with an accuracy less than ±

5 nm.

132. The device according to claim 131, the conducting layer being in suicide or metal or doped Si.

133. The device according to claim 131, further including a layer of insulating material covering the insulating area and the substrate or the conducting layer or the protective layer covering the conducting layer.

135. The device according to claim 131, the semiconducting material being silicon or Si₁₋

xGe_x (0≦

x≦

1).

137. The device according to claim 131, the insulating material of the insulating area being selected from the group consisting of SiO₂, Al₂O₃, AlN, SiON, Si₃N₄, diamond, HfO₂, and a dielectric material with high dielectric constant.