Catalytically enhanced atomic layer deposition process

• US 20070202678A1
• Filed: 02/28/2006
• Published: 08/30/2007
• Est. Priority Date: 02/28/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Han, Joseph, Dominguez, Juan, Lavoie, Adrien, Plombon, John, Simka, Harsono
• Granted Patent: US 7,354,849 B2
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45534 Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A method for carrying out a damascene process to form an interconnect comprises providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer, depositing a copper seed layer onto the adhesion layer using an ALD process, depositing an iodine catalyst layer onto the copper seed layer using an ALD process, and depositing a copper layer onto the copper seed layer using an ALD process. The iodine catalyst layer causes the copper layer to fill the trench by way of a bottom-up fill mechanism. The trench fill is performed using a single ALD process, which minimizes the creation of voids and seams in the final copper interconnect.

Claims

1. A method comprising:

providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer;

depositing a copper seed layer on the adhesion layer;

depositing an iodine catalyst layer on the copper seed layer; and

depositing a copper layer on the copper seed layer, wherein the iodine catalyst layer causes the copper layer to fill the trench by way of a bottom-up fill mechanism.

2. The method of claim 1, further comprising planarizing the copper layer.

3. The method of claim 1, wherein the barrier layer and the adhesion layer are formed using ALD processes.

4. The method of claim 1, wherein a CEALD process is used to deposit the copper seed layer, the iodine catalyst layer, and the copper layer.

5. The method of claim 4, wherein the depositing of the copper seed layer comprises pulsing a copper precursor proximate to the semiconductor substrate, wherein the copper precursor reacts to form the copper seed layer.

6. The method of claim 4, wherein the depositing of the iodine catalyst comprises pulsing an iodine gas proximate to the semiconductor substrate, wherein iodine from the iodine gas is absorbed onto the copper seed layer to form the iodine catalyst layer.

7. The method of claim 4, wherein the depositing of the iodine catalyst comprises pulsing an iodine plasma proximate to the semiconductor substrate, wherein iodine from the iodine plasma is absorbed onto the copper seed layer to form the iodine catalyst layer.

8. The method of claim 4, wherein the depositing of the iodine catalyst comprises pulsing an iodine precursor proximate to the semiconductor substrate, wherein the iodine precursor reacts to form iodine that is absorbed onto the copper seed layer to form the iodine catalyst layer.

9. The method of claim 4, wherein the depositing of the copper layer comprises pulsing a copper precursor proximate to the semiconductor substrate, wherein the copper precursor reacts to form the copper layer.

10. The method of claim 5, wherein the copper precursor comprises Cu(acac)₂ (where acac=acetylacetonato), Cu(thd)₂ (where thd=tetrahydrodionato), hexafluoroacetylacetonate-copper-vinyltrimethylsilane, CpCu(CNMe), CpCu(CNCMe₃), Cp*CuCO, CpCuPR₃ (where R═

Me, Et, or Ph), CpCu(CSiMe₃)₂, MeCu(PPh₃)₃, CuMe, CuCCH(ethynylcopper), CuCMe₃(methylacetylidecopper), (H₂C═

CMeCC)Cu(3-methyl-3-buten-1-ynylcopper), (MCH₂CH₂CC)Cu(1-pentynylcopper), CuCCPh, C₆H₅Cu(phenyl copper), (Me)₃CCCCu(3,3-dimethyl-1-butynyl)copper, (H₃CCH═

CH)₂CuLi, Me₃SiCCCH₂Cu, CuCN, [Cu(OAc)]n (where OAc=acetate), Cu₂Cl₂(butadiene), μ

-[(trimethylsilyl)methyl]copper, C₇H₇CuO(2-methoxyphenylcopper), ([COD]CuCl)₂, (MeCN)₄CuX (where X=a halide, an alkyl, an amine, or a phenyl group), Me₃SiOCu(PMe₃)₃, Cu(C₄H₄S), or a Cu-carbene compound.

11. The method of claim 8, wherein the iodine precursor comprises I₂, C₂H₅I, C₂H₃I, CH₃I, CH₂I₂, or CHI₃.

12. The method of claim 9, wherein the copper precursor comprises Cu(acac)₂ (where acac=acetylacetonato), Cu(thd)₂ (where thd=tetrahydrodionato), hexafluoroacetylacetonate-copper-vinyltrimethylsilane, CpCu(CNMe), CpCu(CNCMe₃), Cp*CuCO, CpCuPR₃ (where R═

Me, Et, or Ph), CpCu(CSiMe₃)₂, MeCu(PPh₃)₃, CuMe, CuCCH(ethynylcopper), CuCMe₃(methylacetylidecopper), (H₂C═

CMeCC)Cu(3-methyl-3-buten-1-ynylcopper), (MCH₂CH₂CC)Cu(1-pentynylcopper), CuCCPh, C₆H₅Cu(phenyl copper), (Me)₃CCCCu(3,3-dimethyl-1-butynyl)copper, (H₃CCH═

CH)₂CuLi, Me₃SiCCCH₂Cu, CuCN, [Cu(OAc)]n (where OAc=acetate), Cu₂Cl₂(butadiene), μ

-[(trimethylsilyl)methyl]copper, C₇H₇CuO(2-methoxyphenylcopper), ([COD]CuCl)₂, (MeCN)₄CuX (where X=a halide, an alkyl, an amine, or a phenyl group), Me₃SiOCu(PMe₃)₃, Cu(C₄H₄S), or a Cu-carbene compound.

13. The method of claim 3, wherein a CEALD process is used to deposit the copper seed layer, the iodine catalyst layer, and the copper layer.

14. A method comprising:

providing a semiconductor substrate having a trench etched into a dielectric layer;

placing the semiconductor substrate within a reaction chamber;

pulsing a barrier layer precursor into the reaction chamber, wherein the barrier layer precursor reacts to form a barrier layer within the trench;

pulsing an adhesion layer precursor into the reaction chamber, wherein the adhesion layer precursor reacts to form an adhesion layer atop the barrier layer;

pulsing a first copper precursor into the reaction chamber, wherein the first copper precursor reacts to form a copper seed layer atop the adhesion layer;

pulsing a catalyst into the reaction chamber, wherein the catalyst forms a catalyst layer that favors collecting on a bottom surface of the trench; and

pulsing a second copper precursor into the reaction chamber, wherein the catalyst layer causes the second copper precursor to react and fill the trench with a copper layer by way of a bottom-up fill mechanism.

15. The method of claim 14, wherein the barrier layer precursor comprises tantalum and nitrogen.

16. The method of claim 14, wherein the adhesion layer precursor comprises tantalum or ruthenium.

17. The method of claim 14, wherein the catalyst comprises iodine.

18. The method of claim 17, wherein the pulsing of the catalyst comprises pulsing an iodine precursor into the reaction chamber, wherein the iodine precursor reacts to form the catalyst layer.

19. The method of claim 18, wherein the iodine precursor comprises I₂, C₂H₅I, C₂H₃I, CH₃I, CH₂I₂, or CHI₃.

20. The method of claim 14, wherein the catalyst comprises bromine.

21. The method of claim 20, wherein the pulsing of the catalyst comprises pulsing a bromine precursor into the reaction chamber, wherein the bromine precursor reacts to form the catalyst layer.

22. The method of claim 21, wherein the bromine precursor comprises Br₂, CH₃Br, or C₂H₅Br.

23. The method of claim 14, wherein the catalyst comprises a catalytic metal.

24. The method of claim 23, wherein the catalytic metal comprises indium acetate, indium acetylacetonate, indium (III) chloride, indium (III) bromide, indium (III) iodide, trimethylindium, tin hydride (SnH₄), tin acetate, tetraethyltin, or tin acetylacetonate.

25. The method of claim 14, wherein the pulsing of the barrier layer precursor, the pulsing of the adhesion layer precursor, the pulsing of the first copper precursor, the pulsing of the catalyst, and the pulsing of the second copper precursor are all performed without removing the semiconductor substrate from the reaction chamber.

26. A method comprising:

providing a semiconductor wafer having a trench etched into a dielectric layer, wherein a barrier layer is formed within the trench and an adhesion layer is formed atop the barrier layer;

placing the semiconductor wafer into a reaction chamber;

introducing a first set of metal precursor pulses into the reaction chamber, wherein the metal precursor reacts to form a metal seed layer atop the adhesion layer;

introducing at least one pulse of a catalyst into the reaction chamber, wherein the catalyst forms a catalyst layer that favors collecting on a bottom surface of the trench;

introducing a second set of metal precursor pulses into the reaction chamber, wherein the catalyst layer causes the metal precursor to react and fill the trench with a metal layer by way of a bottom-up fill mechanism; and

introducing one or more additional pulses of the catalyst during the introduction of the second set of metal precursor pulses, wherein the additional pulses of catalyst are used to modify the bottom-up fill mechanism.

27. The method of claim 26, wherein the metal comprises at least one of copper, gold, and silver.

28. The method of claim 26, wherein the catalyst comprises at least one of iodine, bromine, indium, and tin.

29. The method of claim 26, wherein the second set of metal precursor pulses and the one or more additional pulses of the catalyst are introduced into the reaction chamber in an alternating manner.

30. The method of claim 26, wherein one or more co-reactants are pulsed into the reaction chamber with at least one of the metal precursor and the catalyst.

31. The method of claim 30, wherein the one or more co-reactants comprise at least one of hydrogen, hydrogen plasma, NH₃, silane, B₂H₆, oxygen, and forming gas.

32. The method of claim 26, wherein the catalyst pulse is introduced among the first set of metal precursor pulses.