High performance system-on-chip inductor using post passivation process

• US 20070202685A1
• Filed: 01/30/2007
• Published: 08/30/2007
• Est. Priority Date: 05/27/2003
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Application Number:
  US11/668,484
• Publication Number:
  US 20070202685A1
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A method for fabricating a circuit component comprising:

providing a silicon substrate, a metallization structure over said silicon substrate, and a passivation layer over said metallization structure;

depositing a coil over said passivation layer; and

wirebonding to a metal pad over said silicon substrate, wherein said metal pad is connected to said coil.

2. The method of claim 1, wherein said depositing said coil comprises:

depositing a first metal layer over said passivation layer;

forming a photoresist layer on said first metal layer, an opening in said photoresist layer exposing said first metal layer;

depositing a second metal layer over said first metal layer exposed by said opening;

removing said photoresist layer; and

removing said first metal layer not under said second metal layer.

3. The method of claim 2, wherein said depositing said first metal layer comprises sputtering.

4. The method of claim 2, wherein said depositing said second metal layer comprises electroplating.

5. The method of claim 2, wherein said depositing said first metal layer comprises depositing a titanium-containing layer over said passivation layer.

6. The method of claim 2, wherein said depositing said second metal layer comprises depositing a gold layer over said first metal layer exposed by said opening.

7. The method of claim 1, wherein said depositing said coil comprises:

sputtering a titanium-containing layer with a thickness of between 500 and 5000 angstroms over said passivation layer;

sputtering a first gold layer with a thickness of between 300 and 3000 angstroms on said titanium-containing layer;

forming a photoresist layer on said first gold layer, an opening in said photoresist layer exposing said first gold layer;

electroplating a second gold layer with a thickness of between 1 and 20 micrometers on said first gold layer exposed by said opening;

removing said photoresist layer;

removing said first gold layer not under said second gold layer; and

removing said titanium-containing layer not under said second gold layer.

8. The method of claim 1 further comprising forming a polymer layer over said passivation layer, followed by said depositing said coil on said polymer layer.

9. The method of claim 8, wherein said forming said polymer layer comprises multiple steps of coating, and wherein said coil is provided by a bottommost patterned circuit layer over said passivation layer.

10. The method of claim 1 further comprising forming a polymer layer on said coil, followed by said wirebonding to said metal pad exposed by an opening in said polymer layer.

11. The method of claim 1, wherein said passivation layer comprises nitride.

12. The method of claim 1 further comprising providing a transistor in or on said silicon substrate.

13. A method for fabricating a circuit component comprising:

providing a silicon substrate, a metallization structure over said silicon substrate, and a passivation layer over said metallization structure;

depositing a coil over said passivation layer;

forming a first polymer layer over said coil, an opening in said first polymer exposing a metal pad connected to said coil;

after said forming said first polymer layer, depositing an under bump metallization in said opening; and

after said depositing said under bump metallization, depositing a solder bump connected to said metal pad.

14. The method of claim 13, wherein said depositing said coil comprises:

depositing a first metal layer over said passivation layer;

forming a photoresist layer on said first metal layer, an opening in said photoresist layer exposing said first metal layer;

depositing a second metal layer over said first metal layer exposed by said opening;

removing said photoresist layer; and

removing said first metal layer not under said second metal layer.

15. The method of claim 14, wherein said depositing said first metal layer comprises sputtering.

16. The method of claim 14, wherein said depositing said second metal layer comprises electroplating.

17. The method of claim 14, wherein said depositing said first metal layer comprises depositing a titanium-containing layer over said passivation layer.

18. The method of claim 14, wherein said depositing said second metal layer comprises depositing a gold layer over said first metal layer exposed by said opening.

19. The method of claim 13, wherein said depositing said coil comprises:

sputtering a titanium-containing layer with a thickness of between 500 and 5000 angstroms over said passivation layer;

sputtering a first gold layer with a thickness of between 300 and 3000 angstroms on said titanium-containing layer;

forming a photoresist layer on said first gold layer, an opening in said photoresist layer exposing said first gold layer;

electroplating a second gold layer with a thickness of between 1 and 20 micrometers on said first gold layer exposed by said opening;

removing said photoresist layer;

removing said first gold layer not under said second gold layer; and

removing said titanium-containing layer not under said second gold layer.

20. The method of claim 13 further comprising forming a second polymer layer over said passivation layer, followed by said depositing said coil on said second polymer layer.

21. The method of claim 20, wherein said forming said second polymer layer comprises multiple steps of coating, and wherein said coil is provided by a bottommost patterned circuit layer over said passivation layer.

22. The method of claim 13, wherein said passivation layer comprises nitride.

23. The method of claim 13 further comprising providing a transistor in or on silicon substrate.