Floating-point processor with reduced power requirements for selectable subprecision

• US 20070203967A1
• Filed: 02/27/2006
• Published: 08/30/2007
• Est. Priority Date: 02/27/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Dockser, Kenneth
• Granted Patent: US 8,595,279 B2
• Time in Patent Office: Days
• US Class Current: 708/495
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/49942 Significance control
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision results in one or more excess bits for each of the one or more floating-point numbers. Power may be removed from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits, and the floating-point operation is performed with power removed from the one or more components.

Claims

1. A method of performing a floating-point operation with a floating-point processor having a maximum precision comprising:

selecting a subprecision less than the maximum precision for the floating-point operation on one or more floating-point numbers, the selection of the subprecision resulting in one or more excess bits for each of the one or more floating-point numbers;

removing power from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits; and

performing the floating-point operation with power removed from the one or more components.

2. The method of claim 1 further comprising using a floating-point register with a plurality of storage elements, the one or more excess bits being stored in one or more of the storage elements, and wherein the one or more components from which power is removed includes the storage elements for the one or more excess bits.

3. The method of claim 2 further comprising using a floating-point operator with logic to perform the floating-point operation, and wherein the one or more components from which power is removed includes a portion of the logic that would otherwise be used to process the one or more excess bits.

4. The method of claim 1 further comprising using a floating-point operator with logic to perform the floating-point operation, and wherein the one or more components from which power is removed includes a portion of the logic that would otherwise be used to process the one or more excess bits.

5. The method of claim 4 wherein the floating-point operation comprises addition.

6. The method of claim 5 further comprising forcing a carry-out from the portion of the logic to zero.

7. The method of claim 4 wherein the floating-point operation comprises multiplication.

8. A floating-point processor having a maximum precision comprising:

a floating-point controller configured to select a subprecision less than the maximum precision for a floating-point operation on one or more floating-point numbers, the selection of the subprecision resulting in one or more excess bits for each of the one or more floating-point numbers, the floating-point controller being further configured to remove power from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits; and

a floating-point operator configured to perform the floating-point operation.

9. The floating-point processor of claim 8 further comprising a floating-point register having a plurality of storage elements, the one or more excess bits being stored in one or more of the storage elements, and wherein the one or more components from which power can be removed includes the storage elements for the one or more excess bits.

10. The floating-point processor of claim 9 wherein the floating-point operator comprises logic to perform the floating-point operation, and wherein the one or more components from which power can be removed includes a portion of the logic that would otherwise be used to process the one or more excess bits.

11. The floating-point processor of claim 8 wherein the floating-point operator comprises logic to perform the floating-point operation, and wherein the one or more components from which power can be removed includes a portion of the logic that would otherwise be used to process the one or more excess bits.

12. The floating-point processor of claim 11 wherein the floating-point operator includes a floating-point adder.

13. The floating-point processor of claim 12 wherein the floating-point operator is further configured to force a carry-out from the portion of the logic to zero when the power is removed.

14. The floating-point processor of claim 11 wherein the floating-point operator includes a floating-point multiplier.

15. A floating-point processor having a maximum precision comprising:

a floating-point register having a plurality of storage elements configured to store a plurality of floating-point numbers;

a floating-point operator configured to perform a floating-point operation on the one or more of the floating-point numbers stored in the floating-point register; and

a floating-point controller configured to select a subprecision less than the maximum precision for a floating-point operation on said one or more of the floating-point numbers, the selection of the subprecision resulting in one or more excess bits for each of said one or more of the floating-point numbers, the one or more excess bits being stored in one or more of the storage elements of the floating-point register, and wherein the floating-point controller is further configured to remove power from the storage elements for the one or more excess bits.

16. The floating-point processor of claim 15 wherein the floating-point operator comprises logic configured to perform the floating-point operation, and wherein the floating-point controller is further configured to remove power from a portion of the logic that would otherwise be used to process the one or more excess bits.

17. The floating-point processor of claim 16 wherein the floating-point operator includes a floating-point adder.

18. The floating-point processor of claim 17 wherein the floating-point operator is further configured to force a carry-out from the portion of the logic to zero when the power is removed.

19. The floating-point processor of claim 16 wherein the floating-point operator includes a floating-point multiplier.

20. A floating-point processor having a maximum precision comprising:

a floating-point register configured to store a plurality of floating-point numbers;

a floating-point operator having logic configured to perform a floating-point operation on the one or more of the floating-point numbers stored in the floating-point register; and

a floating-point controller configured to select a subprecision less than the maximum precision for a floating-point operation on said one or more of the floating-point numbers, the selection of the subprecision resulting in one or more excess bits for each of said one or more of the floating-point numbers, and wherein the floating-point controller is further configured to remove power from a portion of the logic that would otherwise be used to process the one or more excess bits.

21. The floating-point processor of claim 20 wherein the floating-register comprises a plurality of storage elements configured to store the floating-point number, the one or more excess bits being stored in one or more of the storage elements, and wherein the floating-point controller is further configured to remove power from the storage elements for the one or more excess bits.

22. The floating-point processor of claim 20 wherein the floating-point operator includes a floating-point adder.

23. The floating-point processor of claim 22 wherein the floating-point operator is further configured to force a carry-out from the portion of the logic to zero when the power is removed.

24. The floating-point processor of claim 20 wherein the floating-point operator includes a floating-point multiplier, and power is removed from portions of elements comprising partial products within the floating-point multiplier.