SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
First Claim
Patent Images
1. A sub-system, comprising:
- an interface circuit capable of communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
3 Assignments
0 Petitions
Accused Products
Abstract
A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
248 Citations
20 Claims
-
1. A sub-system, comprising:
an interface circuit capable of communication with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
17. A method, comprising:
-
interfacing a plurality of memory circuits and a system; and
reducing command scheduling constraints of the memory circuits.
-
-
18. A system, comprising:
-
a plurality of memory circuits, and an interface circuit in communication with the memory circuits, the interface circuit operable to interface the memory circuits for reducing command scheduling constraints of the memory circuits. - View Dependent Claims (19, 20)
-
Specification