Cache memory background preprocessing
First Claim
1. A cache memory preprocessor, for preparing an associative cache memory for use by a processor, said processor being arranged to access a main memory via data caching in said associative memory, said cache memory preprocessor comprising:
- a command inputter, for receiving a multiple-way cache memory processing command from said processor; and
a command implementer associated with said command inputter, for performing background processing upon multiple ways of said cache memory in accordance with said multiple-way cache memory processing command.
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Abstract
A cache memory preprocessor prepares a cache memory for use by a processor. The processor accesses a main memory via a cache memory, which serves a data cache for the main memory. The cache memory preprocessor consists of a command inputter, which receives a multiple-way cache memory processing command from the processor, and a command implementer. The command implementer performs background processing upon multiple ways of the cache memory in order to implement the cache memory processing command received by the command inputter.
205 Citations
49 Claims
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1. A cache memory preprocessor, for preparing an associative cache memory for use by a processor, said processor being arranged to access a main memory via data caching in said associative memory, said cache memory preprocessor comprising:
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a command inputter, for receiving a multiple-way cache memory processing command from said processor; and
a command implementer associated with said command inputter, for performing background processing upon multiple ways of said cache memory in accordance with said multiple-way cache memory processing command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A background memory refresher, for updating main memory data in a main memory in accordance with data cached in a cache memory, wherein said cache memory is arranged in blocks, comprising:
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a command inputter, for receiving a block update command; and
a block updater, associated with said command inputter, for performing background update operations blockwise from a specified block of said cache memory so as to update said main memory in accordance with data cached in said specified block of said cache memory. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A cache memory background block preloader, for preloading main memory data arranged in blocks into a cache memory, comprising:
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a command inputter, for receiving a block initialize command; and
a cache initializer, for performing blockwise background caching of data of a specified block of main memory into said cache memory. - View Dependent Claims (24, 25)
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26. A system, for processing data from a segmented memory, comprising:
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a segmented memory comprising a plurality of memory segments, said memory segments comprising a respective data section and a respective cache memory section;
a processor, for processing data, performing read and write operations to said segmented memory, and for controlling processing system components, and being arranged to access a memory segment via data caching in the respective cache memory section;
a cache memory preprocessor, associated with said processor, for preparing said cache memory sections for use by said processor by performing background processing upon multiple ways of at least one of said cache memory sections in accordance with a multiple-way cache memory processing command received from said processor; and
a switching grid-based interconnector associated with said segmented memory, for providing in parallel switchable connections between said processor and said cache memory preprocessor to selectable ones of said memory segments. - View Dependent Claims (27)
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28. A method for preparing a cache memory, by:
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receiving a cache memory processing command to specify background processing of multiple ways of said cache memory; and
performing background processing upon multiple ways of said cache memory so as to implement said cache memory processing command. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A method for updating main memory data from cached data in a cache memory, wherein said cache memory is arranged in blocks, by:
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receiving a block update cache memory processing command; and
performing background update operations blockwise from a cache memory block specified in said command, so as to update said main memory in accordance with data cached in said specified block within said cache memory - View Dependent Claims (39)
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40. A method for caching main memory data of a main memory into a cache memory, wherein said main memory is arranged in blocks, by:
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receiving a block initialize cache memory processing command; and
performing background blockwise caching of data of a main memory block specified in said command into said cache memory. - View Dependent Claims (41)
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- 42. A program instruction for cache memory block preprocessing, recorded or transmitted as a signal in or via a tangible medium, said signal comprising operands defining a cache memory blockwise processing operation and a memory block upon which said processing operation is to be performed.
- 46. A computer running a compiler which compiles a program instruction for cache memory block preprocessing into executable instruction sequences, said sequences comprising instructions from a predefined set of instructions, wherein said instruction set comprises a cache memory block preprocessing instruction having operands defining a cache memory blockwise processing operation and a memory block for performing said processing operation upon, and having low priority so as to prevent the execution of said preprocessing instruction from interfering with higher priority commands.
Specification