Moveable locked lines in a multi-level cache

• US 20070204121A1
• Filed: 02/24/2006
• Published: 08/30/2007
• Est. Priority Date: 02/24/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morrow, Michael, O'Connor, Dennis, Strazdus, Stephen
• Granted Patent: US 8,533,395 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel

Abstract

A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.

Claims

1. A method to cache information in a multi-level cache hierarchy, comprising:

locking a cache line by attaching a lock indication property to a cache line; and

allowing the lock indication property to remain associated with the cache line that is moved within the multi-level cache hierarchy.

2. The method of claim 1 further including using, at each level of the multi-level cache hierarchy, the lock indication property to protect the cache line from being overwritten when space for new data is needed.

3. The method of claim 1 further including not restricting the locked cache line to a particular level in the multi-level cache hierarchy.

4. The method of claim 1 further including copying the cache line to another cache and the lock indication property associated with the cache line moves to the another cache.

5. The method of claim 1, wherein locking a cache line further includes not evicting the cache line back to a main memory unless a cache controller first receives a command to unlock the cache line.

6. The method of claim 1, wherein the lock indication property associated with the cache line further includes assuring that the locked cache line is in an inner cache, an outer cache, or both.

7. A method comprising:

locking a line into a cache without fixing the line into a location in a multi-level cache hierarchy.

8. The method of claim 7, wherein locking a line into the cache further includes guaranteeing the line is in at least one of the caches within the multi-level cache hierarchy.

9. The method of claim 7, wherein locking a line into the cache further includes not specifying which cache in the multi-level cache hierarchy or which line in the cache.

10. The method of claim 7, wherein locking a line into the cache further includes associating a lock property with the cache line to indicate the cache line is not a preferred cache line for replacement if memory space is needed for new cache data.

11. A method comprising:

evicting a cache line from a first level of the cache memory hierarchy to a second level of the cache memory hierarchy; and

transferring a lock property corresponding to the cache line to the second level of the cache memory hierarchy.

12. The method of claim 11, wherein data in the cache line in the second level of the cache memory hierarchy, when accessed, is not evicted to a main memory in accordance with the lock property transferred with the cache line.

13. The method of claim 12, wherein the second level of the cache memory hierarchy examines the lock property as set for the cache line in the first level to determine whether to evict the cache line to the main memory.

14. A method comprising:

evicting a cache line from a first level of a cache memory hierarchy to a second level of the cache memory hierarchy; and

evaluating the evicted line to determine a lock property; and

transferring the lock property corresponding to the evicted line to the second level of the cache memory hierarchy

15. The method of claim 14, wherein data in the cache line in the second level of the cache memory hierarchy, when accessed, is not evicted to a main memory in accordance with the lock property transferred with the cache line.

16. The method of claim 15, wherein the second level of the cache memory hierarchy examines the lock property as set for the cache line in the first level to determine whether to evict the cache line to the main memory.

17. A system including a multi-level cache hierarchy, comprising:

a processor to evict a cache line from a first level of the multi-level cache hierarchy to a second level and to transfer a lock property associated with the cache line to the second level of the multi-level cache hierarchy.

18. The system of claim 17, wherein the processor includes two processor cores each having the multi-level cache hierarchy.

19. The system of claim 17, wherein caches in the hierarchy are shared between the two processor cores.

20. The system of claim 17, further including first and second antenna coupled to a transceiver to transfer signals with the processor.

21. The system of claim 17, wherein the second level of the multi-level cache hierarchy is a unified cache.

22. A processor having multi-level cache hierarchy comprising:

a first level data cache where cache lines have an associated lock property;

a first level instruction cache where cache lines have an associated lock property; and

an outer level cache that receives a cache line evicted from the first level data cache or the first level instruction cache and a decision on what action to take with the cache line is based on the lock property that remains associated with the cache line.

23. The processor of claim 22 wherein the outer level cache is a unified cache.

24. The processor of claim 22 further including first and second processor cores each having the multi-level cache hierarchy.

25. The processor of claim 24 wherein caches in the hierarchy are shared between the first and second processor cores.