Multimedia Three-Dimensional Memory (M3DM) System
First Claim
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1. A multimedia three-dimensional memory (M3DM), comprising:
- a three-dimensional memory (3D-M) comprising a substrate and a plurality of vertically stacked memory levels;
wherein said 3D-M stores at least one movie at an average storage cost per movie comparable to DVD, and said movie has been recorded in said 3D-M before said 3D-M is distributed to a user.
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Abstract
Among all semiconductor memory technologies, three-dimensional memory (3D-M), particularly mask-programmable 3D-M (3D-MPM), has the largest storage capacity and is the only one that can store movies at a reasonable price. Accordingly, the present invention discloses a multimedia three-dimensional memory (M3DM).
24 Citations
20 Claims
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1. A multimedia three-dimensional memory (M3DM), comprising:
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a three-dimensional memory (3D-M) comprising a substrate and a plurality of vertically stacked memory levels;
wherein said 3D-M stores at least one movie at an average storage cost per movie comparable to DVD, and said movie has been recorded in said 3D-M before said 3D-M is distributed to a user. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multimedia three-dimensional memory (M3DM) system, comprising:
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a three-dimensional memory (3D-M) comprising a substrate and a plurality of vertically stacked memory levels, said 3D-M containing a plurality of pre-recorded multimedia contents (PMC);
an access-control block for controlling access to said PMC; and
a mobile device for playing back selected multimedia contents from said PMC;
wherein said PMC have been recorded in said 3D-M before said 3D-M is distributed to a user. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A narrow-line three-dimensional memory, comprising:
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a substrate having a transistor-based memory, said transistor-based memory comprising a plurality of first address-selection lines in parallel; and
a diode-based memory stacked above and coupled to said substrate through a plurality of inter-level vias, said diode-based memory comprising a plurality of second address-selection lines in parallel;
wherein the minimum pitch of said second address-selection lines is smaller than said first address-selection lines, and the minimum feature-size of said diode-based memory is smaller than contemporary transistor-based memory. - View Dependent Claims (17, 18, 19, 20)
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Specification