Distributive scoreboard scheduling in an out-of order processor

• US 20070204135A1
• Filed: 02/28/2006
• Published: 08/30/2007
• Est. Priority Date: 02/28/2006
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Jiang, Xing
• Granted Patent: US 7,721,071 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a distributive scoreboard for each instruction. The appended operand availability bits are propagated together with the instruction through multiple stages of the processor pipeline. An instruction dispatch buffer stores the instruction and the operand availability bits. A dispatch controller determines when an instruction is to be issued. The determination is based, at least in part, on the operand availability bits stored in the instruction dispatch buffer.

Claims

1. An instruction dispatch unit for a processor, comprising:

control logic that appends a plurality of operand availability bits to an instruction;

an instruction buffer that stores the instruction and a plurality of the operand availability bits; and

an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer.

2. The instruction dispatch unit of claim 1, wherein the operand availability bits are propagated together with the instruction through a plurality of pipeline stages.

3. The instruction dispatch unit of claim 1, wherein the plurality of operand availability bits include a counter value.

4. The instruction dispatch unit of claim 1, wherein the plurality of operand availability bits include a value to activate a counter.

5. The instruction dispatch unit of claim 1, wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.

6. The instruction dispatch unit of claim 5, wherein the register is one of a general purpose register, an accumulator register and a co-processor register.

7. The instruction dispatch unit of claim 1, wherein the plurality of operand availability bits include a value to indicate predictable availability of a source operand of the instruction in a completion buffer.

8. The instruction dispatch unit of claim 1, wherein the control logic includes a renaming map.

9. A processor core comprising:

an instruction dispatch unit that includes;

control logic that appends a plurality of operand availability bits to an instruction;

an instruction buffer that stores the instruction and a plurality of the operand availability bits; and

an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer.

10. The processor core of claim 9, wherein the operand availability bits are propagated together with the instruction through a plurality of pipeline stages.

11. The processor core of claim 9, wherein the plurality of operand availability bits include a counter value.

12. The processor core of claim 9, wherein the plurality of operand availability bits include a value to activate a counter.

13. The processor core of claim 9, wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.

14. The processor core of claim 13, wherein the register is one of a general purpose register, an accumulator register and a co-processor register.

15. The processor core of claim 9, wherein the plurality of operand availability bits include a value to indicate predictable availability of a source operand of the instruction in a completion buffer

16. The processor core of claim 9, wherein the control logic includes a renaming map.

17. A computer readable storage medium comprising a processor core having an out-of-order pipeline embodied in software, the processor core comprising:

an instruction dispatch unit that includes;

control logic that appends a plurality of operand availability bits to an instruction;

an instruction buffer that stores the instruction and a plurality of the operand availability bits; and

an instruction dispatcher that determines when the instruction is issued to an execution unit of the processor based, at least in part, on the plurality of operand availability bits stored in the instruction buffer.

18. The computer readable storage medium of claim 17, wherein the operand availability bits are propagated together with the instruction through a plurality of pipeline stages.

19. The computer readable storage medium of claim 17, wherein the plurality of operand availability bits include a counter value.

20. The computer readable storage medium of claim 17, wherein the plurality of operand availability bits include a value to activate a counter.

21. The computer readable storage medium of claim 17, wherein the plurality of operand availability bits include a value to indicate availability of a source operand of the instruction in a register.

22. The computer readable storage medium of claim 21, wherein the register is one of a general purpose register, an accumulator register and a co-processor register.

23. The computer readable storage medium of claim 17, wherein the plurality of operand availability bits include a value to indicate predictable availability of a source operand of the instruction in a completion buffer.

24. The computer readable storage medium of claim 17, wherein the control logic includes a renaming map.

25. The computer readable storage medium of claim 17, wherein the processor core is embodied in hardware description language software.

26. The computer readable storage medium of claim 17, wherein the processor core is embodied in Verilog hardware description language software.

27. The computer readable storage medium of claim 17, wherein the processor core is embodied in VHDL hardware description language software.