Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture

• US 20070204137A1
• Filed: 08/23/2006
• Published: 08/30/2007
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Thang
• Granted Patent: US 7,890,735 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel

Abstract

A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Claims

1. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

first and second decode pipelines;

first and second execute pipelines; and

coupling circuitry operable in a first mode to couple first and second threads from said first and second decode pipelines to said first and second execute pipelines respectively, and said coupling circuitry operable in a second mode to couple the first thread to both said first and second execute pipelines.

2. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

first and second instruction dependency scoreboards;

first and second instruction input coupling circuits each having a coupling input and first and second coupling outputs and together operable to selectively feed said first and second instruction dependency scoreboards; and

output coupling logic having first and second coupling inputs fed by said first and second scoreboards, and having first and second instruction issue outputs.

3. A telecommunications unit comprising:

a wireless modem; and

a multi-threaded microprocessor for processing instructions of a real-time phone call-related thread and a non-real-time thread, said microprocessor coupled to said wireless modem and said microprocessor comprising;

a fetch unit;

first and second decode pipelines coupled to said fetch unit;

first and second execute pipelines; and

coupling circuitry operable in a first mode to couple the real-time phone call-related thread and non-real-time thread from said first and second decode pipelines to said first and second execute pipelines respectively, and said multiplexer circuitry operable in a second mode to couple the real-time phone call-related thread to both said first and second execute pipelines; and

a microphone coupled to said multi-threaded microprocessor.

4. A multi-threaded microprocessor for processing instructions in threads, comprising:

a fetch unit having a branch target buffer for sharing by the threads;

first and second decode pipelines coupled to said fetch unit;

first and second execute pipelines respectively coupled to said first and second decode pipelines to execute threads; and

first and second thread-specific register files respectively coupled to said first and second execute pipelines.

5. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

an instruction issue unit;

at least two execute pipelines coupled to said instruction issue unit;

at least two register files;

a storage for first thread identifications corresponding to each register file and second thread identifications corresponding to each execute pipeline; and

coupling circuitry responsive to the first thread identifications and to the second thread identifications to couple each said execute pipeline to each said register file for which the first and second thread identifications match.

6. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

a processor pipeline for the instructions;

a first storage coupled to said processor pipeline and operable to hold first information for access by a first thread and second information for access by a second thread;

a storage for a thread security configuration; and

a hardware state machine responsive to said storage for thread security configuration to protect the first information in said first storage from access by the second thread depending on the thread security configuration.

7. A multi-threaded microprocessor for processing instructions in threads, the microprocessor comprising:

at least one processor pipeline for the instructions;

a storage for a thread power management configuration; and

a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads.

8. A telecommunications unit comprising:

a limited-energy source;

a wireless modem coupled to said limited energy source;

a multi-threaded microprocessor coupled to said limited energy source and to said wireless modem and said microprocessor operable for processing instructions in threads and including at least one processor pipeline for the instructions, a storage for a thread power management configuration, and a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads; and

a microphone coupled to said multi-threaded microprocessor.

9. A multi-threaded processor for processing instructions of plural threads, the processor comprising:

first and second decode pipelines;

issue circuitry respectively coupled to said first and second decode pipelines;

first and second execute pipelines respectively coupled to said issue circuitry to execute instructions of threads;

a shared execution unit coupled to said issue circuitry; and

a busy-control circuit coupled to said issue circuitry and operable to prevent issue of an instruction from one of the threads to operate the shared execute unit when the shared execute unit is busy executing an instruction from another of the threads.

10. A multi-threaded processor for processing instructions of plural threads, the processor comprising:

a fetch unit having branch prediction circuitry;

first and second parallel pipelines coupled to said fetch unit and operable for encountering branch instructions in either thread for prediction by said branch prediction circuitry;

said branch prediction circuitry including at least two global history registers (GHRs) for different threads and a shared global history buffer (GHB) to supply branch prediction information.

11. A multi-threaded processor for processing instructions of plural threads, the processor comprising:

first and second issue queues;

issue circuitry respectively coupled at least to said first and second issue queues;

first and second execute pipelines respectively coupled to said issue circuitry to execute instructions of threads; and

control circuitry having a first single thread active line for dual issue to said first and second execute pipelines based from the first issue queue being primary, and a second single thread active line for dual issue to said first and second execute pipelines based from the second issue queue being primary, and for controlling multithreading by independent single-issue of threads to said first and second execute pipelines respectively.

12. A multi-threaded processor for processing instructions of plural threads, the processor comprising:

first and second decode pipelines;

issue circuitry respectively coupled at least to said first and second decode pipelines;

first and second execute pipelines respectively coupled to said issue circuitry to execute instructions of the threads; and

control circuitry having a storage for thread priorities and enabled thread identifications and responsive to select at least first and second highest priority enabled threads as first and second selected threads, and to launch the first selected thread into the first decode pipeline and launch the second selected thread into the second decode pipeline.

13. A process of manufacturing a multithreaded processor comprising:

preparing design code representing a multi-threaded superscalar processor having thread-specific security and thread-specific power management and thread-specific issue scoreboarding;

verifying that the thread-specific security prevents forbidden accesses between threads and verifying that the thread-specific power management circuitry selectively delivers thread-specific power controls; and

fabricating units of the multithreaded superscalar processor.

14. A multi-threaded microprocessor for processing instructions of threads, the microprocessor comprising:

at least one execute pipeline for executing the instructions of threads;

at least two register files for data respective to at least two threads and coupled to said at least one execute pipeline; and

a scratch memory coupled to at least one said register file for transfer of data from the at least one said register file to said scratch memory and data for at least one additional thread from said scratch memory to the at least one said register file.