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Masking process for simultaneously patterning separate regions

  • US 20070205438A1
  • Filed: 03/02/2006
  • Published: 09/06/2007
  • Est. Priority Date: 03/02/2006
  • Status: Active Grant
First Claim
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1. A method comprising:

  • patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask;

    patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask; and

    patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask, wherein the sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

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