Masking process for simultaneously patterning separate regions

• US 20070205438A1
• Filed: 03/02/2006
• Published: 09/06/2007
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,842,558 B2
• Time in Patent Office: Days
• US Class Current: 257/216
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Claims

1. A method comprising:

patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask;

patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask; and

patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask, wherein the sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

2. The method of claim 1, wherein the sacrificial layer comprises polycrystalline silicon.

3. The method of claim 1, wherein the first plurality of semiconductor structures are recessed into the semiconductor substrate.

4. The method of claim 1, wherein the first plurality of semiconductor structures are recessed below the second plurality of semiconductor structures.

5. The method of claim 1, wherein the first plurality of semiconductor structures are U-shaped transistor structures.

6. The method of claim 1, wherein the second plurality of semiconductor structures are planar transistor structures.

7. The method of claim 1, further comprising performing an ion implantation technique to dope selected portions of the first semiconductor structures.

8. The method of claim 1, wherein the second plurality of semiconductor structures comprises a polycrystalline silicon region.

9. The method of claim 8, wherein the second plurality of semiconductor structures further comprises a gate dielectric layer positioned between the logic portion of the semiconductor substrate and the polycrystalline silicon region.

10. The method of claim 1, wherein the second plurality of semiconductor structures comprises a silicide region.

11. The method of claim 1, wherein patterning the first plurality of semiconductor structures over the array portion of the semiconductor substrate comprises:

forming a plurality of elongate shallow trenches; and

forming a plurality of elongate deep trenches positioned substantially parallel to the plurality of elongate shallow trenches.

12. The method of claim 11, wherein forming the plurality of elongate shallow trenches and the plurality of elongate deep trenches comprises performing a pitch multiplication process.

13. The method of claim 11, wherein patterning the first plurality of semiconductor structures over the array portion of the semiconductor substrate further comprises filling the elongate shallow trenches and the elongate deep trenches with an oxide material.

14. The method of claim 1, wherein the semiconductor substrate comprises single crystal silicon.

15. The method of claim 1, further comprising depositing a conformal insulating layer over the second plurality of semiconductor structures.

16. The method of claim 15, wherein:

patterning the sacrificial layer comprises forming a plurality of gaps in the sacrificial layer, the gaps having a gap spacing; and

the conformal insulating layer has a thickness that is at least half the gap spacing.

17. The method of claim 15, further comprising etching the conformal insulating layer from horizontal surfaces in the array and logic portions of the semiconductor substrate.

18. The method of claim 17, wherein etching the conformal insulating layer forms a plurality of sidewall spacers adjacent the second plurality of semiconductor structures over the logic portion of the semiconductor substrate.

19. The method of claim 15, wherein the conformal insulating layer comprises silicon nitride.

20. The method of claim 1, further comprising using the patterned sacrificial layer to define a hard mask over the array portion of the semiconductor substrate.

21. The method of claim 20, further comprising removing the patterned sacrificial layer after defining the hard mask.

22. The method of claim 21, further comprising etching a plurality of trenches through the hard mask and into the array portion of the semiconductor substrate after removing the patterned sacrificial layer.

23. The method of claim 22, further comprising forming a plurality of elongate sidewall spacers adjacent to vertical sidewalls of the plurality of trenches etched into the array portion of the semiconductor substrate.

24. The method of claim 23, wherein the plurality of elongate sidewall spacers comprises a semiconductor material.

25. The method of claim 23, further comprising an oxide layer positioned between the plurality of elongate spacers and the vertical sidewalls of the plurality of trenches etched into the array portion of the semiconductor substrate.

26. A method comprising:

providing a semiconductor substrate having a first region and a second region;

depositing a conductive layer over the substrate first and second regions;

patterning the conductive layer deposited over the substrate first and second regions;

using the patterned conductive layer to form a planar transistor structure over the substrate second region; and

using the patterned conductive layer in a masking process in the substrate first region.

27. The method of claim 26, wherein the semiconductor substrate comprises single crystal silicon.

28. The method of claim 26, wherein the conductive layer comprises polycrystalline silicon.

29. The method of claim 28, wherein the conductive layer further comprises a silicide material positioned over the polycrystalline silicon.

30. The method of claim 28, wherein the conductive layer further comprises an oxide layer positioned between the polycrystalline silicon and the semiconductor substrate.

31. The method of claim 26, further comprising using the patterned conductive layer as a sacrificial material to define a hard mask over the substrate first region.

32. The method of claim 31, further comprising:

depositing a hard mask material over the sacrificial material; and

removing a portion of the sacrificial material to form a pattern of alternating regions of hard mask material and sacrificial material over the substrate first region.

33. The method of claim 32, further comprising removing the sacrificial material from over the substrate first region.

34. The method of claim 33, further comprising etching a pattern of elongate trenches into the substrate first region, wherein the pattern of elongate trenches is defined by the regions of hard mask material.

35. The method of claim 34, further comprising forming a plurality of elongate silicon regions in the elongate trenches.

36. A partially-formed integrated circuit comprising:

a first plurality of features comprising a first material and formed over a first portion of a substrate, wherein the first plurality of features are separated from each other by a first spacing;

a second plurality of features comprising a second material and formed over a second portion of the substrate, wherein the first plurality of features and the second plurality of features are formed simultaneously, and wherein the first material is the same as the second material;

a gap fill structure positioned between and contacting a selected two of the first plurality of features; and

a plurality of sidewall spacers positioned adjacent the second plurality of features, wherein adjacent sidewall spacers are separated from each other by a separation region, and wherein the plurality of sidewall spacers and the gap fill structure comprise the same material.

37. The partially-formed integrated circuit of claim 36, wherein the first and second portions of the substrate comprise single crystal silicon.

38. The partially-formed integrated circuit of claim 36, wherein the first portion of the substrate comprises:

a plurality of elongate shallow trenches;

a plurality of elongate deep trenches positioned substantially parallel to the plurality of elongate shallow trenches; and

a plurality of elongate silicon regions that separate the plurality of elongate shallow trenches and the plurality of elongate deep trenches.

39. The partially-formed integrated circuit of claim 38, wherein the plurality of elongate silicon regions include a doped region used to form a U-shaped transistor structure.

40. The partially-formed integrated circuit of claim 39, wherein the plurality of elongate shallow trenches separate a first source/drain region of the U-shaped transistor from a second source/drain region of the U-shaped transistor.

41. The partially-formed integrated circuit of claim 38, wherein the first and second plurality of features comprise elongate polycrystalline silicon features that cross the plurality of elongate shallow trenches.

42. The partially-formed integrated circuit of claim 38, wherein the plurality of elongate shallow trenches and the plurality of elongate deep trenches are filled with an oxide material.

43. The partially-formed integrated circuit of claim 36, wherein the first portion of the substrate includes a region of doped single crystal silicon.

44. The partially-formed integrated circuit of claim 36, wherein the second plurality of features are separated from each other by a second spacing that is larger than the first spacing.

45. The partially formed integrated circuit of claim 44, wherein the second spacing is between about two times and about four times larger than the first spacing.

46. The partially-formed integrated circuit of claim 36, wherein the first and second plurality of features comprise elongate gate stacks.

47. The partially-formed integrated circuit of claim 46, wherein the first and second plurality of features comprise a silicide region positioned over a polycrystalline silicon region.

48. The partially-formed integrated circuit of claim 46, wherein the first and second plurality of features comprise a gate dielectric layer positioned under a polycrystalline silicon region.

49. The partially-formed integrated circuit of claim 36, wherein the first and second plurality of features comprise polycrystalline silicon.

50. The partially-formed integrated circuit of claim 36, wherein:

the first plurality of features form a pattern of sacrificial material; and

the second plurality of features forms part of a plurality of final structures positioned over the second portion of the substrate.

51. The partially-formed integrated circuit of claim 50, wherein the plurality of final structures are planar transistors.

52. The partially-formed integrated circuit of claim 50, wherein the plurality of sidewall spacers function as a plurality of insulating spacers for the plurality of final structures.

53. The partially-formed integrated circuit of claim 36, wherein the gap fill structure forms a portion of a hard mask pattern.

54. The partially-formed integrated circuit of claim 53, wherein the hard mask pattern defines trenches for a U-shaped transistor structure.

55. The partially-formed integrated circuit of claim 36, wherein the gap fill structure and the sidewall spacers comprise silicon nitride.

56. A memory device comprising:

a substrate having an array portion and a logic portion;

a plurality of semiconductor structures that are recessed in the array portion of the substrate;

a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure, and wherein the transistor devices are formed in a layer that is below the plurality of semiconductor structures.

57. The memory device of claim 56, wherein each of the plurality of semiconductor devices occupies an area of the substrate array portion between about 4 F² and about 8 F², wherein F is the minimum resolvable feature size formable using a photolithographic technique that is used to define features of the semiconductor structures.

58. The memory device of claim 57, wherein each of the plurality of semiconductor devices occupies an area of the substrate having a length dimension that is not equal to a width dimension.

59. The memory device of claim 57, wherein each of the plurality of semiconductor devices occupies an area of the substrate having a length dimension that is equal to a width dimension.

60. The memory device of claim 56, wherein the plurality of semiconductor devices form a pattern having a first pitch, and wherein the plurality of transistor devices form a pattern having a second pitch that is at least two times the first pitch.

61. The memory device of claim 56, wherein the plurality of transistor devices are formed using a photolithographic mask that is also simultaneously used to pattern at least a portion of the plurality of semiconductor structures recessed in the array portion of the substrate.

62. The memory device of claim 56, wherein the plurality of semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches.

63. The memory device of claim 62, wherein the alternating deep and shallow trenches are filled with an oxide material.

64. The memory device of claim 62, wherein the alternating deep and shallow trenches are filled with a spin-on dielectric material.

65. The memory device of claim 62, wherein the shallow trenches are at least partially filled with a semiconductor material.

66. The memory device of claim 56, wherein the semiconductor structures include a channel portion that is contiguous with the substrate array portion.

67. The memory device of claim 56, wherein the substrate comprises single crystal silicon.

68. The memory device of claim 56, wherein the plurality of transistor devices formed over the logic portion of the substrate are planar transistor devices.

69. The memory device of claim 56, wherein the plurality of transistor devices formed over the logic portion of the substrate include a silicide region positioned over the uncapped gate layer.

70. The memory device of claim 69, wherein the silicide region comprises a material selected from the group consisting of tungsten silicide and titanium silicide.