Vertical gated access transistor

• US 20070205443A1
• Filed: 03/02/2006
• Published: 09/06/2007
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,476,933 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.

Claims

1. A method of forming an apparatus, the method comprising:

forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate, wherein at least one of the shallow trenches is positioned between two deep trenches, and wherein the plurality of shallow trenches and the plurality of deep trenches are parallel to each other;

depositing a layer of conductive material over the first region and a second region of the substrate;

etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate;

masking the second region of the substrate;

removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed; and

etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.

2. The method of claim 1, wherein the elongate trenches cross the plurality of deep trenches and the plurality of shallow trenches.

3. The method of claim 1, wherein the elongate trenches have an intermediate depth as compared to the deep trenches and the shallow trenches.

4. The method of claim 1, wherein the layer of conductive material comprises a layer of polycrystalline silicon and a layer of metallic material.

5. The method of claim 4, wherein the layer of metallic material comprises tungsten silicide.

6. The method of claim 1, further comprising:

depositing an insulating material over the first region and the second region of the substrate after etching the plurality of elongate trenches;

planarizing the insulating material to expose the conductive material in the second region;

depositing a metal layer over the substrate, such that the metal layer contacts the exposed conductive material in the second region; and

creating a silicide region of the conductive material.

7. The method of claim 6, wherein the metal layer comprises titanium and the silicide region comprises titanium silicide.

8. The method of claim 1, further comprising forming a plurality of elongate sidewall spacers in the elongate trenches, wherein the elongate sidewall spacers comprise gate electrode material.

9. The method of claim 8, wherein two elongate sidewall spacers are formed in each elongate trench.

10. The method of claim 1, further comprising depositing a spacer material along the plurality of lines in the first region of the substrate, and along the plurality of active device elements in the second region of the substrate, wherein the spacer material deposited in the second region of the substrate forms a sidewall spacer structure.

11. The method of claim 10, wherein the spacer material comprises silicon nitride.

12. The method of claim 10, wherein the spacer material fills the plurality of gaps in the first region of the substrate, such that the plurality of lines are separated by a plurality of gaps filled with the spacer material.

13. The method of claim 12, wherein, after the plurality of lines are removed from the first region of the substrate, the plurality of exposed areas are separated by a plurality of regions of spacer material.

14. The method of claim 13, wherein the plurality of regions of spacer material defines a mask for etching the plurality of trenches.

15. The method of claim 1, wherein the plurality of deep trenches and the plurality of shallow trenches are formed before the plurality of elongate trenches are etched.

16. The method of claim 1, wherein the active device elements are transistor gate stacks each having an oxide layer and a polycrystalline silicon region without an insulating cap formed thereover.

17. The method of claim 1, wherein the active device elements comprise a silicide material positioned over a polycrystalline silicon material.

18. The method of claim 1, wherein the substrate comprises single crystal silicon.

19. The method of claim 1, further comprising forming a layer of dielectric material over the first region and the second region of the substrate before depositing the layer of conductive material thereover.

20. The method of claim 1, wherein the plurality of deep trenches are separated from the plurality of shallow trenches by a portion of the substrate.

21. The method of claim 20, wherein the portion of the substrate separating the plurality of deep trenches from the plurality of shallow trenches comprises doped single crystal silicon.

22. The method of claim 20, wherein the portion of the substrate separating the plurality of deep trenches from the plurality of shallow trenches has a width of between about ½

F and about ¾

F, wherein F corresponds to a minimum feature size formable using a photolithographic technique.

23. An apparatus comprising:

a semiconductor substrate having an array portion and a logic portion;

at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate; and

at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions.

24. The apparatus of claim 23, wherein the at least one transistor device is a planar transistor.

25. The apparatus of claim 23, wherein the first and second source/drain regions further comprise a region of doped semiconductor material.

26. The apparatus of claim 23, wherein a first U-shaped semiconductor structure is separated from a second U-shaped semiconductor structure by a deep trench, wherein the deep trench is deeper than a shallow trench that separates the first pillar from the second pillar.

27. The apparatus of claim 26, wherein the deep trench and the shallow trench are filled with an oxide material.

28. The apparatus of claim 23, further comprising a spacer formed adjacent to a vertical sidewall of the at least one transistor device.

29. The apparatus of claim 28, wherein the spacer comprises a nitride material.

30. The apparatus of claim 28, wherein the spacer has a width that is greater than or equal to half of a width of the first pillar.

31. The apparatus of claim 23, further comprising an elongate spacer formed adjacent to the U-shaped semiconductor structure.

32. The apparatus of claim 31, wherein the elongate spacer is formed in an intermediate-depth trench that is deeper than a shallow trench that separates the first pillar from the second pillar.

33. The apparatus of claim 31, wherein the elongate spacer is separated from the U-shaped semiconductor structure by an oxide layer.

34. The apparatus of claim 31, wherein the elongate spacer comprises a conductive gate material.

35. The apparatus of claim 31, wherein the elongate spacer crosses a shallow trench that separates the first pillar from the second pillar.

36. The apparatus of claim 23, wherein the at least one transistor device does not include an insulating cap layer formed thereover.

37. The apparatus of claim 23, further comprising an shallow trench positioned between the first and second pillars.

38. The apparatus of claim 23, wherein the gate dielectric layer comprises an oxide material.

39. The apparatus of claim 23, wherein the gate material comprises a polycrystalline silicon material.

40. The apparatus of claim 39, the gate material further comprises a metal silicide.

41. The apparatus of claim 40, wherein the metal silicide comprises a material selected from the group consisting of tungsten silicide and titanium silicide.

42. The apparatus of claim 23, further comprising:

a capacitor formed over the first source/drain region; and

an insulated bit line formed over the second source/drain region.

43. A memory device comprising:

a substrate having an array portion and a logic portion;

a plurality of U-shaped semiconductor structures that are formed in the array portion of the substrate, wherein the U-shaped semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches; and

a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure.

44. The memory device of claim 43, wherein the plurality of transistor devices are formed using a photolithographic mask that is also simultaneously used to pattern at least a portion of the plurality of U-shaped semiconductor structures over the array portion of the substrate.

45. The memory device of claim 43, wherein the alternating deep and shallow trenches are filled with an oxide material.

46. The memory device of claim 43, wherein the alternating deep and shallow trenches are filled with a spin-on dielectric material.

47. The memory device of claim 43, wherein the shallow trenches are at least partially filled with a conductive gate material.

48. The memory device of claim 43, wherein the U-shaped semiconductor structures include a channel portion that is contiguous with the substrate array portion.

49. The memory device of claim 43, wherein the substrate comprises single crystal silicon.

50. The memory device of claim 43, wherein the plurality of transistor devices formed over the logic portion of the substrate are planar transistor devices.

51. The memory device of claim 43, wherein the plurality of transistor devices formed over the logic portion of the substrate include a silicide region positioned over the uncapped gate layer.

52. The memory device of claim 51, wherein the silicide region comprises a material selected from the group consisting of tungsten silicide and titanium silicide.

53. A method comprising:

patterning a plurality of shallow trenches and a plurality of deep trenches in a substrate array region;

patterning a plurality of intermediate-depth trenches in the substrate array region, wherein the intermediate-depth trenches cross the shallow and deep trenches, wherein the intermediate-depth, shallow and deep trenches define a plurality of U-shaped transistor structures in the substrate array region, and wherein the plurality of intermediate-depth trenches are defined by a photolithography mask; and

patterning a plurality of planar transistor structures in a substrate logic region, wherein the plurality of planar transistor structures are defined by the photolithography mask.

54. The method of claim 53, wherein:

at least one of the shallow trenches is positioned between two deep trenches; and

the plurality of shallow trenches and the plurality of deep trenches are parallel to each other.

55. The method of claim 53, further comprising:

depositing an insulating material over the substrate array and logic regions after patterning the plurality of intermediate-depth trenches;

planarizing the insulating material to expose the planar transistor structures in the logic region;

depositing a metal layer over the substrate, such that the metal layer contacts the plurality of exposed planar transistor structures; and

reacting the metal with the exposed planar transistor structures.

56. The method of claim 55, wherein the metal layer comprises titanium and the silicide region comprises titanium silicide.

57. The method of claim 53, further comprising forming a plurality of sidewall spacers adjacent to the plurality of planar transistor structures in the substrate logic region.

58. The method of claim 57, wherein the plurality of sidewall spacers comprises silicon nitride.

59. The method of claim 57, wherein forming the plurality of sidewall spacers further comprises simultaneously defining a hard mask for the plurality of intermediate-depth trenches in the substrate array region.

60. The method of claim 59, wherein the plurality of sidewall spacers and the mask comprise the same material.

61. The method of claim 53, wherein the plurality of planar transistor structures comprises a gate stack including silicon over a gate dielectric.

62. The method of claim 61, wherein the gate stack includes a strapping region of silicide material over the silicon.

63. The method of claim 62, wherein the strapping region of silicide material comprises a material selected from the group consisting of tungsten silicide and titanium silicide.

64. The method of claim 53, wherein the intermediate-depth trenches are substantially perpendicular to the shallow and deep trenches.

65. The method of claim 53, further comprising filing the plurality of shallow trenches and the plurality of deep trenches with a spin-on dielectric material.

66. The method of claim 53, further comprising filing the plurality of shallow trenches and the plurality of deep trenches with an insulating material.

67. The method of claim 53, further comprising forming a plurality of elongate conductive sidewall spacers in the intermediate-depth trenches.

68. The method of claim 67, wherein the plurality of elongate conductive sidewall spacers comprise a semiconductor material.

69. The method of claim 53, wherein the plurality of U-shaped transistor structures include a source region, a drain region and a channel connecting the source and drain regions, wherein the channel is contiguous with the substrate.

70. The method of claim 69, wherein the source and the drain regions are formed atop first and second pillar portions of the plurality of U-shaped transistors, respectively.

71. The method of claim 69, wherein the source and the drain regions comprise a doped semiconductor material.