Dynamically controlled power reduction method and circuit for a graphics processor

• US 20070206018A1
• Filed: 03/03/2006
• Published: 09/06/2007
• Est. Priority Date: 03/03/2006
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Fry, James, Bajic, Ljubisa
• Granted Patent: US 8,102,398 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.

Claims

1. A method of operating a graphics accelerator comprising:

in response to detecting a desired reduced power mode, limiting a frame rendering rate of a graphics processor to an adjusted frame rendering rate equal to or less than a frame refresh rate of a display interconnected with said graphics processor and rendering graphics to be displayed on said display, at said adjusted frame rendering rate;

controlling operation of said graphics processor so that idle time of said graphics processor between rendering frames is controlled.

2. The method of claim 1, wherein said controlling comprises controlling operation of said graphics processor so that idle time of said graphics processor reaches a pre-programmed value.

3. The method of claim 2, wherein said pre-programmed value is less than about ½

of said frame adjusted frame rendering rate

4. The method of claim 2, wherein said pre-programmed value is less than about ¼

of said frame rendering rate.

5. The method of claim 2, wherein said pre-programmed value is less than about 1/10 of said frame rendering rate.

6. The method of claim 1, wherein said controlling further comprises adjusting a clock frequency of an operating clock of said graphics processor.

7. The method of claim 6, wherein said operating clock is an operating clock for a graphics engine of said graphics processor.

8. The method of claim 7, wherein said controlling further comprises adjusting a supply voltage to said graphics engine of said graphics processor.

9. The method of claim 7, further comprising adjusting a bias voltage applied to a substrate of said graphics processor.

10. The method of claim 6, further comprising generating a signal indicative of said graphics processor idling, and wherein said controlling comprises generating an error signal representative of the desired idle time, and the actual idle time of said graphics processor.

11. The method of claim 10, further comprising filtering said signal indicative of said graphics processor idling to generate a control signal for controlling said operating clock of said graphics processor.

12. The method of claim 11, wherein said filtering comprises filtering said signal indicative of said processor idling signal using an N-tap FIR filter.

13. The method of claim 8, wherein adjusting said supply voltage comprises using a look-up table to determine a voltage in dependence on said clock frequency.

14. The method of claim 9, wherein adjusting said bias voltage comprises using a look-up table to determine a back bias voltage in dependence on at least one of said clock frequency and said supply voltage.

15. A graphics accelerator comprising:

a graphics engine for rendering graphical images to be displayed on a display;

an adjustable clock source, for providing an operating clock signal to said graphics engine;

a controller in communication with said graphics engine and said adjustable clock source, to control a frequency of said adjustable clock source so that said graphics engine remains idle for a desired time between frames as said graphics engine renders frames.

16. The graphics accelerator of claim 15, further comprising a controllable voltage supply to supply an operating voltage to said graphics engine, and wherein said controller is further in communication with said controllable voltage supply to adjust said operating voltage in dependence on said frequency of said adjustable clock source.

17. The graphics accelerator of claim 16, further comprising a second controllable voltage supply to supply a back bias voltage to a substrate of said graphics engine, and wherein said controller is further in communication with said controllable voltage supply to adjust said back bias voltage in dependence on at least one of said frequency of said adjustable clock source and said operating voltage.

18. The graphics accelerator of claim 17, wherein said controller comprises a multi-tap FIR filter to filter idle time over multiple frames.

19. The graphics accelerator of claim 17, wherein said controller adjusts said clock in increments, and wherein said increments vary in dependence on said error.

20. The graphics accelerator of claim 16, further comprising a look-up table used to determine said operating voltage.

21. The graphics accelerator of claim 17, further comprising a look-up table used to determine said back bias voltage.

22. A computing device comprising the graphics accelerator of claim 15.

23. A computing device comprising:

means for rendering graphics frames;

means for, in response to detecting a reduced power condition, limiting a frame generation rate of said means for rendering to an adjusted frame generation rate equal to or less than a frame refresh rate of a display interconnected with said means for rendering;

means for controlling operation of said means for rendering so that idle time of said means for rendering between rendered frames is reduced.