Dynamically controlled power reduction method and circuit for a graphics processor
First Claim
1. A method of operating a graphics accelerator comprising:
- in response to detecting a desired reduced power mode, limiting a frame rendering rate of a graphics processor to an adjusted frame rendering rate equal to or less than a frame refresh rate of a display interconnected with said graphics processor and rendering graphics to be displayed on said display, at said adjusted frame rendering rate;
controlling operation of said graphics processor so that idle time of said graphics processor between rendering frames is controlled.
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Accused Products
Abstract
A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.
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Citations
23 Claims
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1. A method of operating a graphics accelerator comprising:
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in response to detecting a desired reduced power mode, limiting a frame rendering rate of a graphics processor to an adjusted frame rendering rate equal to or less than a frame refresh rate of a display interconnected with said graphics processor and rendering graphics to be displayed on said display, at said adjusted frame rendering rate;
controlling operation of said graphics processor so that idle time of said graphics processor between rendering frames is controlled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A graphics accelerator comprising:
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a graphics engine for rendering graphical images to be displayed on a display;
an adjustable clock source, for providing an operating clock signal to said graphics engine;
a controller in communication with said graphics engine and said adjustable clock source, to control a frequency of said adjustable clock source so that said graphics engine remains idle for a desired time between frames as said graphics engine renders frames. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A computing device comprising:
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means for rendering graphics frames;
means for, in response to detecting a reduced power condition, limiting a frame generation rate of said means for rendering to an adjusted frame generation rate equal to or less than a frame refresh rate of a display interconnected with said means for rendering;
means for controlling operation of said means for rendering so that idle time of said means for rendering between rendered frames is reduced.
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Specification