NAND MEMORY DEVICE COLUMN CHARGING

• US 20070206422A1
• Filed: 03/01/2006
• Published: 09/06/2007
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie
• Granted Patent: US 7,436,708 B2
• Time in Patent Office: Days
• US Class Current: 365/185.250
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.

Claims

1. A method of operating a NAND flash memory device comprising:

powering up the memory device in response to an externally supplied power;

charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level following powering up; and

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level.

2. The method of claim 1 wherein the read operation comprises:

accessing a row of memory cells by activating a word line conductor of the first data page; and

sensing a voltage potential of column bit lines of the first data page after accessing the row.

3. The method of claim 2 further comprising charging all column bit lines of the first data page to the predetermined positive voltage level following sensing the voltage potential of the column bit lines of the first data page.

4. The method of claim 1 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

5. The method of claim 1 wherein the predetermined positive voltage level is about one volt.

6. A method of operating a NAND flash memory device comprising:

charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level prior to performing an array access operation; and

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level.

7. The method of claim 6 further comprising powering up the memory device in response to an externally supplied power, and wherein charging all column bit lines of the first and second data pages is performed as a step of powering up the memory device.

8. The method of claim 6 wherein the read operation comprises:

accessing a row of memory cells by activating a word line conductor of the first data page; and

sensing a voltage potential of column bit lines of the first data page after accessing the row.

9. The method of claim 8 further comprising charging all column bit lines of the first data page to the predetermined positive voltage level following sensing the voltage potential of the column bit lines of the first data page.

10. The method of claim 6 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

11. A method of operating a NAND flash memory device comprising:

powering up the memory device in response to an externally supplied power;

charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level following powering up;

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level, wherein the read operation comprises accessing a row of memory cells by activating a word line conductor of the first data page, and sensing a voltage potential of column bit lines of the first data page after accessing the row; and

re-charging all column bit lines of the first data page to the predetermined positive voltage level following sensing the voltage potential of the column bit lines of the first data page.

12. The method of claim 11 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

13. A NAND flash memory device comprising:

an array of memory cells arranged in accessible rows and columns, wherein each column of memory cells are coupled to a corresponding bit line; and

control circuitry to perform a read operation on a column of the array of memory cells, wherein the read operation comprises sensing a voltage level of the bit line associated with the column being read, and charging the bit line to a predetermined voltage following sensing the voltage level of the bit line.

14. The NAND flash memory device of claim 13 wherein the control circuitry charges the bit line to the predetermined voltage during a power-up operation of the memory device.

15. The NAND flash memory device of claim 13 wherein the control circuitry maintains a charge on first and second adjacent bit lines located adjacent to and on opposite lateral sides of the bit line associated with the column being read while sensing the voltage level.

16. The NAND flash memory device of claim 13 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

17. The NAND flash memory device of claim 13 wherein the predetermined voltage is provided by a voltage regulator circuit.

18. A NAND flash memory device comprising:

an array of memory cells arranged in accessible rows and columns, wherein each column of memory cells are coupled to an associated bit line; and

control circuitry to perform a power-up operation on the memory in response to externally provided power, wherein the power-up operation comprises charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level prior to initiating an array access operation.

19. The NAND flash memory device of claim 18 wherein the control circuitry performs a read operation on a column of the array of memory cells, wherein the read operation comprises sensing a voltage level of a bit line associated with the column being read, and charging the bit line to the predetermined voltage following sensing the voltage level of the bit line.

20. The NAND flash memory device of claim 18 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

21. The NAND flash memory device of claim 18 wherein the control circuitry maintains a charge on first and second adjacent bit lines located adjacent to and on opposite lateral sides of the bit line associated with the column being read while sensing the voltage level.

22. The NAND flash memory device of claim 18 wherein the predetermined voltage is provided by a voltage regulator circuit.

23. A flash memory device comprising:

an array of memory cells having a column format arrangement, wherein each column of cells is coupled to a bit line, the bit lines arranged to form a first page and a second page; and

circuitry to apply a voltage to the columns to reduce a column coupling capacitance.

24. The flash memory device of claim 23, wherein the circuitry is to apply a single voltage to the columns.

25. The flash memory device of claim 23, wherein the circuitry is to maintain a positive voltage level on all the bit lines prior to read, write, and program operations.

26. The flash memory device of claim 23, wherein the bit lines are arranged in an alternating pattern such that every other bit line is coupled together to form one of the first page or the second page.

27. The flash memory device of claim 23, wherein the bit lines associated with the first page and the bit lines associated with the second page are to receive from the circuitry substantially identical voltages.

28. A method of improving data read timing comprising:

pre-charging all bit lines of a first page and a second page of a flash memory to a specified positive voltage level, the bit lines formed in a staggered arrangement; and

performing a logical operation on an active page while all column bit lines of the inactive page are maintained at the positive voltage level.

29. The method of claim 28, wherein performing includes performing a memory access operation.

30. The method of claim 29, wherein pre-charging includes re-charging all bit lines after performing a logical operation.

31. The method of claim 29, wherein pre-charging includes re-charging all bit lines before performing a next logical operation

32. The method of claim 29, wherein pre-charging includes pre-charging to reduce a current surge during the logical operation.

33. A flash device comprising:

a plurality memory cells arranged in columns along bit lines, the bit lines are coupled to form logical pages; and

a charging device to provide a positive voltage level to the bit lines prior to initiating a memory access operation to reduce a transient current output from the charging device.

34. The flash device of claim 33, wherein the charging device is to further provide the positive voltage level to improve data read timing.

35. The flash device of claim 33, wherein the positive voltage to the bit lines is to reduce an effective column coupling capacitance.

36. The flash device of claim 33, wherein the logical pages are interwoven using an alternating bit line arrangement.

37. The flash device of claim 36, wherein the logical pages include an active page and an inactive page, and wherein positive voltage to the bit lines associated with the inactive page is maintained during the memory access operation.

38. The flash device of claim 33, wherein the charging device is coupled to a memory controller.

39. The flash device of claim 33, wherein the charging device is to provide the positive voltage level when the memory cells receive power.

40. The flash device of claim 33, wherein the bit lines receive the positive voltage level at power-up, read execution and verify operations.

41. The flash device of claim 34, wherein the bit lines are coupled to receive logical information provided to one or more word lines during the memory access operation.