Encoding and deserialization-serialization for digital signals

• US 20070206641A1
• Filed: 09/11/2006
• Published: 09/06/2007
• Est. Priority Date: 11/10/2005
• Status: Abandoned Application

• Current Assignee: X-EMI, Inc.
• Original Assignee: X-EMI, Inc.
• Inventors: Egan, Kenneth W.
• Application Number:
  US11/519,210
• Publication Number:
  US 20070206641A1
• Time in Patent Office: Days
• US Class Current: 370/479
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 2370/12 Use of DVI or HDMI protocol in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/0175 Coupling arrangements; Interface arrangements interface arrangements for digital computers G06F3/00, G06F13/00
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

Transmit-side active signal management circuitry applies one or more active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.

Claims

1. An apparatus comprising:

a plurality of conductive interconnects; and

a first cable receptacle comprising;

a first housing;

a first receptacle interface coupleable to an interface of a first device;

a deserializer configured to generate a first plurality of parallel digital signals based on an input serialized digital signal; and

a serializer configured to generate an output serialized digital signal based on a second plurality of parallel digital signals, wherein the second plurality of parallel digital signals is based on the first plurality of parallel digital signals.

2. The apparatus of claim 1, further comprising:

an encoder/decoder configured to generate at least a subset of the second plurality of parallel digital signals based on at least a subset of the first plurality of parallel digital signals.

3. The apparatus of claim 2, wherein the encoder/decoder comprises:

a noise source configured to provide a digital noise signal; and

a modification module configured to modify a digital signal of the first plurality of parallel digital signals based on the digital noise signal to generate a corresponding digital signal of the second plurality of parallel digital signals.

4. The apparatus of claim 2, wherein the encoder/decoder comprises:

a symbol encoder configured to encode at least one occurrence of a substantially periodic data symbol of a digital signal of the first plurality of parallel digital signals to generate a digital signal of the second plurality of parallel digital signals.

5. The apparatus of claim 2, wherein the encoder/decoder comprises:

a symbol decoder configured to decode at least one encoded occurrence of a substantially periodic data symbol of a digital signal of the first plurality of parallel digital signals to generate a digital signal of the second plurality of parallel digital signals.

6. The apparatus of claim 2, wherein the encoder/decoder comprises:

An encryption module configured to encrypt a digital signal of the first plurality of parallel digital signals to generate a digital signal of the second plurality of parallel digital signals.

7. The apparatus of claim 2, wherein the encoder/decoder comprises:

a decryption module configured to decrypt a digital signal of the first plurality of parallel digital signals to generate a digital signal of the second plurality of parallel digital signals.

8. The apparatus of claim 1, wherein the first serialized signal comprises a digital video signal.

9. The apparatus of claim 1, comprising:

an integrated circuit, the integrated circuit comprising the serializer and the deserializer.

10. The apparatus of claim 1, wherein the apparatus comprises one of:

a cable;

and a cable adaptor.

11. The apparatus of claim 1, wherein the cable receptacle comprises one of:

a Digital Video Interface (DVI) compatible cable receptacle;

a High Definition Multimedia Interface (HDMI) compatible cable receptacle;

a DisplayPort compatible cable receptacle;

a Universal Display Interface (UDI) compatible cable receptacle;

a Universal Serial Bus (USB) compatible cable receptacle; and

a FireWire compatible cable receptacle.

12. A method comprising:

receiving, at a cable receptacle of a cable assembly, a first serialized digital signal;

deserializing, at the cable receptacle, the first serialized digital signal to generate a first plurality of parallel digital signals; and

serializing, at the cable receptacle, a second plurality of parallel digital signals to generate a second serialized digital signal, wherein the second plurality of parallel digital signals is based on the first set of parallel digital signals.

13. The method of claim 12, further comprising:

providing an output digital signal from the cable receptacle to a device coupled to the cable receptacle, the output digital signal based on the second serialized digital signal.

14. The method of claim 12, further comprising:

providing an output digital signal from the cable receptacle to another cable receptacle of the cable assembly via at least one conductive interconnect of the cable assembly.

15. The method of claim 12, further comprising:

modifying at least a subset of the first plurality of parallel digital signals to generate at least a subset of the second plurality of parallel digital signals.

16. The method of claim 15, wherein modifying comprises modifying a digital signal of the first set of parallel digital signals based on a digital noise signal to generate a corresponding digital signal of the second set of parallel digital signals.

17. The method of claim 15, wherein modifying comprises encoding at least one occurrence of a substantially periodic data symbol of a digital signal of the first set of parallel digital signals to generate a corresponding digital signal of the second set of parallel digital signals.

18. The method of claim 15, wherein modifying comprises decoding at least one encoded occurrence of a substantially periodic data symbol of a digital signal of the first set of parallel digital signals to generate a corresponding digital signal of the second set of parallel digital signals.

19. The method of claim 15, wherein modifying comprises encrypting a digital signal of the first set of parallel digital signals to generate a corresponding digital signal of the second set of parallel digital signals.

20. The method of claim 15, wherein modifying comprises decrypting a digital signal of the first set of parallel digital signals to generate a corresponding digital signal of the second set of parallel digital signals.

21. An apparatus comprising:

a transition minimized differential signaling (TMDS) decoder comprising an input configured to receive a first TMDS encoded signal and an output configured to provide a first TMDS decoded signal based on the first TMDS encoded signal;

an electromagnetic interference (EMI) encoder/decoder comprising an input configured to receive the first TMDS decoded signal and an output configured to provide a second TMDS decoded signal, wherein the EMI encoder is configured to generate the second TMDS decoded signal based on the first TMDS decoded signal and a digital noise signal; and

a TMDS encoder comprising an input configured to receive the second TMDS decoded signal and an output configured to provide a second TMDS encoded signal based on the second TMDS decoded signal.

22. The apparatus of claim 21, wherein the first TMDS encoded signal comprises a digital video signal.

23. The apparatus of claim 22, comprising:

an integrated circuit, the integrated circuit comprising the TMDS decoder, the EMI encoder, and the TMDS encoder.

24. A method comprising:

receiving a first transition minimized digital signaling (TMDS) encoded signal;

decoding the first TMDS encoded signal to generate a first TMDS decoded signal;

modifying the first TMDS decoded signal based on a digital noise signal to generate a second TMDS decoded signal; and

encoding the second TMDS decoded signal to generate a second TMDS encoded signal.

25. The method of claim 24, wherein:

receiving the first TMDS encoded signal comprises receiving the first TMDS encoded signal at a cable receptacle of a cable apparatus;

decoding the first TMDS encoded signal comprises decoding the first TMDS at the cable receptacle;

modifying the first TMDS decoded signal comprises modifying the first TMDS decoded signal at the cable receptacle; and

encoding the second TMDS decoded signal comprises encoding the second TMDS decoded signal at the cable receptacle.

26. A cable apparatus comprising:

a first cable receptacle comprising;

a first receptacle interface couplable to an interface of a first device; and

a first port configured to receive a first transitional minimized differential signal (TMDS) encoded digital signal;

a second port configured to provide a second TMDS encoded signal based on the first TMDS encoded digital signal;

a first TMDS decoder comprising an input configured to receive a third TMDS encoded signal and an output configured to provide a first TMDS decoded signal based on the third TMDS encoded signal, wherein the third TMDS encoded signal is based on the first TMDS encoded signal;

a first EMI encoder comprising an input configured to receive the first TMDS decoded signal and an output configured to provide a second TMDS decoded signal, wherein the first EMI encoder is configured to generate the second TMDS decoded signal based on the first TMDS decoded signal and a first digital noise signal; and

a first TMDS encoder comprising an input configured to receive the second TMDS decoded signal and an output configured to provide a fourth TMDS encoded signal based on the second TMDS decoded signal, wherein the second TMDS encoded signal is based on the fourth TMDS encoded signal.

27. The cable apparatus of claim 26, further comprising:

a second cable receptacle comprising;

a second receptacle interface couplable to an interface of a second device; and

a third port configured to receive the second TMDS encoded signal;

a fourth port configured to provide a fifth TMDS encoded signal based on the second TMDS encoded digital signal;

a second TMDS decoder comprising an input configured to receive a sixth TMDS encoded signal and an output configured to provide a third TMDS decoded signal based on the sixth TMDS encoded signal, wherein the sixth TMDS encoded signal is based on the second TMDS encoded signal;

a second EMI encoder comprising an input configured to receive the second TMDS decoded signal and an output configured to provide a third TMDS decoded signal, wherein the second EMI encoder is configured to generate the third TMDS decoded signal based on the second TMDS decoded signal and a second digital noise signal, the second digital noise signal representative of the first digital noise signal; and

a second TMDS encoder comprising an input configured to receive the third TMDS decoded signal and an output configured to provide a seventh TMDS encoded signal based on the third TMDS decoded signal, wherein the fifth TMDS encoded signal is based on the seventh TMDS encoded signal.

28. The cable apparatus of claim 26, wherein the cable apparatus comprises one of:

a cable interconnect or a cable adapter.

29. The cable apparatus of claim 26, wherein the first digital signal comprises a digital video signal.

30. The cable apparatus of claim 29, wherein the first cable receptacle comprises one of:

a Digital Video Interface (DVI) compatible cable receptacle;

a High Definition Multimedia Interface (HDMI) compatible cable receptacle;

a DisplayPort compatible cable receptacle; and

a Universal Display Interface (UDI) compatible cable receptacle.