Method and system for providing low cost robust operational control of video encoders

• US 20070206674A1
• Filed: 03/01/2006
• Published: 09/06/2007
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Streaming Networks PVT Limited
• Original Assignee: Streaming Networks PVT Limited
• Inventors: ul-Haq, Imran, Ziauddin, Syed Muhammad, Nadeem, Muhammad, Shafique, Muhammed
• Granted Patent: US 7,912,123 B2
• Time in Patent Office: Days
• US Class Current: 375/240.50
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/147 according to rate distortion criteria rate-distortion as a criterion for motion estimation H04N19/567
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/154 Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion use of rate-distortion criteria H04N19/147
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/174 the region being a slice, e.g. a line of blocks or a group of blocks
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

In one aspect, the present invention discloses a simple low cost framework for robust operational control of video encoders. The framework comprises a two-layer architecture that effectively decouples the processes of video bit rate control and video quality/distortion control. The upper layer includes a video bit rate controller that operates on a single picture/picture-slice, or a set of pictures/picture-slices, and is based on feedback control techniques used in automatic control systems. The lower layer includes a video quality/distortion controller that operates at the level of blocks of pixels, and reduces distortion artifacts. The decoupled nature of the encoder control architecture of the present invention provides the flexibility of combining various feedback control algorithms and various distortion reduction schemes. In another aspect, the present invention discloses an efficient bit rate controller that serves as the upper layer of the operational control architecture, and is based on the proportional-integral-derivative (PID) technique used in automatic control systems. The bit rate controller relies on pure feedback of bit rate data and does not require rate-distortion modeling. In yet another aspect, the present invention discloses a simple and effective video quality/distortion controller that serves as the lower layer of the operational control architecture, and is based upon factors that directly influence the human visual system (HVS). The quality/distortion controller relies on very simple image distortion, complexity and activity metrics and does not depend upon rate-distortion optimization techniques. The low cost video encoder operational control architecture of the present invention may be used in connection with H.264 (ISO/IEC 14496-10) compliant video encoders as well as other video coding standards.

Claims

1. A system for handling video encoding, the system comprising:

a bit rate controller configured to operate at a picture/slice level and generate a plurality of quantization parameters based on feedback control;

a quality/distortion controller configured to receive the plurality of quantization parameters, operate at a pixel block level and generate a plurality of quality/distortion control signals; and

a video encoder configured to receive the plurality of quantization parameters and the plurality of quality/distortion control signals and generate a bit rate signal;

wherein the feedback control is based on the bit rate signal.

2. The system of claim 1 wherein the bit rate controller is further configured to operate in an adaptive or non-adaptive manner based on the feedback control.

3. The system of claim 1 wherein the system is implemented in software or hardware or a combination of both.

4. The system of claim 1 wherein the bit rate controller includes a proportional-integral-derivative (PID) controller with fixed gains operating in accordance with the feedback control, and wherein the values of the fixed gains are predetermined.

5. The system of claim 1 wherein the bit rate controller includes a proportional-integral-derivative (PID) controller with variable gains operating in accordance with the feedback control, and wherein the values of the variable gains are updated during operation.

6. The system of claim 1 further comprising a video encoder buffer;

and

wherein state information with respect to the video encoder buffer is used to control the bit rate controller in order to prevent buffer overflow and/or underflow.

7. The system of claim 1 wherein information with respect to selection of picture/slice types is used to control the bit rate controller.

8. The system of claim 1 wherein the bit rate controller is further configured to operate within a single pass video encoding system or a multiple pass video encoding system.

9. The system of claim 1 wherein the video encoder is further configured to encode on a real-time or non-real-time basis and generate data streams at a constant bit rate or at a variable bit rate.

10. The system of claim 1 wherein the quality/distortion controller is further configured to operate on the basis of data relating to a human visual system (HVS), the data including measures of brightness, variance, distortion, or motion activity in a single pixel block or a plurality of pixel blocks.

11. The system of claim 1 wherein the measures of brightness, variance, distortion, or motion activity used in the operation of the quality/distortion controller are obtained from a plurality of video images, their scaled-down versions, or their sub-sampled versions.

12. The system of claim 1 further comprising a video encoder buffer;

and

wherein state information with respect to the video encoder buffer is used to control the quality/distortion controller in order to prevent buffer overflow and/or underflow.

13. The system of claim 1 wherein the quality/distortion controller is further configured to handle a plurality of processes including pixel block mode selection, pixel block partition selection, or pixel block quantizer selection;

and

wherein the plurality of processes are handled based on a plurality of comparisons of human visual system (HVS) data with a plurality of HVS constants and functions.

14. The system of claim 13 wherein the plurality of HVS constants and functions are predetermined.

15. The system of claim 13 wherein the plurality of processes are handled on a binary basis.

16. The system of claim 1 wherein the system is in compliant with one of a plurality of video coding standards including H.264/AVC, VC-1, MPEG-4, MPEG-2, MPEG-1 and H.263.