Method and system for all digital gain control

• US 20070206684A1
• Filed: 05/03/2007
• Published: 09/06/2007
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Kazakevich, Leonid, Yang, Rui
• Granted Patent: US 7,391,814 B2
• Time in Patent Office: Days
• US Class Current: 375/243
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 7/06 having semiconductor devices
• CPC Class Codes: H03M 1/1235 Non-linear conversion not otherwise provided for in subgroups of H03M1/12

Abstract

An analog/digital gain control device avoid some of the requirements associated with the nature of a closed-loop AGC circuits and which meets the remaining requirements without much difficulty uses an analog to digital conversion method that increases the number of effective ADC bits by compressing the baseband input analog signal using a logarithmic circuit. After the compressed analog signal is converted into a digital signal, a digital anti-log process or look-up table (LUT) is used to expand the digital signal back to the original linear scale. The word size of the output of the anti-log process is larger than the input word size due to the nature of the anti-log function. To reduce the word size of the digital signal an open loop normalization technique can be applied.

Claims

1. A gain controller for obtaining wide range and high resolution analog-to-digital conversion of an in-phase (I) signal and a quadrature (Q) signal, the gain controller comprising:

(a) a first low pass filter configured to generate a filtered I signal;

(b) a second low pass filter configured to generate a filtered Q signal; and

(c) a normalization circuit coupled to outputs of the first and second low pass filters for adjusting the gain of the filtered I and Q signals on a block-by-block basis as a function of averaged combined signal strength measurements of the filtered I and Q signals.

2. The gain controller of claim 1 further comprising:

(d) a first analog compressor for compressing the I signal into a compressed analog I signal;

(e) a first analog-to digital (A/D) converter electrically coupled to an output of the first analog compressor for converting the compressed analog I signal into a compressed digital I signal;

(f) a first expander electrically coupled to an output of the first A/D converter and an input of the first low pass filter, the first expander configured to expand the compressed digital I signal back to an original linear scale;

(g) a second analog compressor for compressing the Q signal into a compressed analog Q signal;

(h) a second A/D converter electrically coupled to an output of the second analog compressor for converting the compressed analog Q signal into a compressed digital Q signal; and

(i) a second expander electrically coupled to an output of the second A/D converter and an input of the second low pass filter, the second expander configured to expand the compressed digital Q signal back to an original linear scale.

3. The gain controller of claim 2 wherein the first and second compressors are logarithmic amplifiers.

4. The gain controller of claim 2 wherein the first and second expanders are anti-log look-up tables (LUTs).

5. The gain controller of claim 1 wherein the normalization circuit reduces word size of the filtered I and Q signals.

6. The gain controller of claim 1 wherein each of the first and second low pass filters is a root-raised cosine (RRC) filter.

7. The gain controller of claim 1 wherein each of the first and second low pass filters is an infinite impulse response (IIR) filter.

8. The gain controller of claim 2 further comprising:

(j) a first delay circuit electrically coupled to an output of the first low pass filter for outputting a delayed filtered I signal;

(k) a second delay circuit electrically coupled to an output of the second low pass filter for outputting a delayed filtered Q signal;

(l) a first multiplier having a first input electrically coupled to an output of the first delay circuit, and a second input electrically coupled to an output of the normalization circuit used to adjust the gain of the delayed filtered I signal, wherein the first multiplier outputs a value substantially equal to the delayed filtered I signal divided by the averaged combined signal strength of the filtered I and Q signals; and

(m) a second multiplier having a first input electrically coupled to an output of the second delay circuit, and a second input electrically coupled to an output of the normalization circuit used to adjust the gain of the delayed filtered Q signal, wherein the second multiplier outputs a value substantially equal to the delayed filtered Q signal divided by the averaged combined signal strength of the filtered I and Q signals.

9. A gain control method employed in a communication system for obtaining wide range and high resolution analog-to-digital conversion of an in-phase (I) signal and a quadrature (Q) signal, the method comprising:

(a) filtering a digital I signal to generate a filtered I signal;

(b) filtering a digital Q signal to generate a filtered Q signal; and

(c) adjusting the gain of the filtered I and Q signals on a block-by-block basis as a function of averaged combined power measurements of the filtered I and Q signals.

10. The method of claim 9 further comprising:

(d) compressing the I signal into a compressed analog I signal;

(e) converting the compressed analog I signal into a compressed digital I signal;

(f) expanding the compressed digital I signal back to an original linear scale;

(g) compressing the Q signal into a compressed analog Q signal;

(h) converting the compressed analog Q signal into a compressed digital Q signal; and

(i) expanding the compressed digital Q signal back to an original linear scale.

11. The method of claim 10 wherein the I signal is logarithmically compressed into the compressed analog I signal at baseband.

12. The method of claim 10 wherein the Q signal is logarithmically compressed into the compressed analog Q signal at baseband.

13. The method of claim 10 wherein the compressed digital I signal is logarithmically expanded.

14. The method of claim 10 wherein the compressed digital Q signal is logarithmically expanded.

15. The method of claim 10 further comprising:

(j) delaying the filtered I signal to generate a delayed filtered I signal;

(k) delaying the filtered Q signal to generate a delayed filtered Q signal;

(l) dividing the delayed filtered I signal by the averaged combined signal strength of the filtered I and Q signals; and

(m) dividing the delayed filtered Q signal by the averaged combined signal strength of the filtered I and Q signals.