METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE

• US 20070207578A1
• Filed: 05/01/2007
• Published: 09/06/2007
• Est. Priority Date: 09/21/2001
• Status: Active Grant

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oda, Hidekazu, OTA, Kazunobu, Sayama, Hirokazu
• Granted Patent: US 7,531,402 B2
• Time in Patent Office: Days
• US Class Current: 438/231
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;

(b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region and forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively;

(c) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes;

(d) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode;

(e) forming a second offset sidewall with a silicon oxide film on said first offset sidewall;

(f) ion implanting said P-type impurity into said first PMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.

2. A method of manufacturing a semiconductor device comprising the steps of:

(a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a second NMOS region for forming a second NMOS transistor with a higher operating voltage than said first NMOS transistor;

(b) selectively forming a first gate insulating film in both said first NMOS region and said second NMOS region;

(c) selectively forming a first gate insulating film greater in thickness than said first gate insulating film on said second NMOS region;

(d) forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and on said second gate insulating film of said second NMOS region, respectively;

(e) forming a first silicon oxide film whole surface of the silicon substrate and anisotropically etching back the first silicon oxide film to form a first offset sidewall on side surface of said first and second gate electrodes;

(d) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode;

(e) forming a second offset sidewall with a silicon oxide film on said first offset sidewall;

(f) ion implanting said N-type impurity into said second NMOS region using said second gate electrode and said first and second offset sidewall as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.