Method of forming an MOS transistor and structure therefor

• US 20070207582A1
• Filed: 03/06/2006
• Published: 09/06/2007
• Est. Priority Date: 03/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon, Robb, Francine
• Granted Patent: US 7,282,406 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.

Claims

1. An MOS transistor comprising:

a substrate having a first conductivity type;

a body region of the transistor formed as a first doped region of a second conductivity type in the substrate and electrically coupled to a conductor;

an opening extending into the substrate and into the first doped region, the opening having a sidewall; and

a gate structure of the MOS transistor within the opening, the gate structure including a first insulator having a first thickness along a first portion of the sidewall and also including a second insulator having a second thickness along another portion of the sidewall wherein the second thickness is greater than the first thickness.

2. The MOS transistor of claim 1 further including a gate conductor within the opening and juxtaposed to the first insulator.

3. The MOS transistor of claim 1 further including a second doped region of the first conductivity type overlying the first doped region and wherein the first insulator is juxtaposed to a portion of the first doped region and the second insulator is juxtaposed a portion of the second doped region.

4. The MOS transistor of claim 3 further including a third doped region of the first conductivity type overlying a portion of the second doped region.

5. The MOS transistor of claim 4 wherein the third doped region is spaced a first distance away from the second insulator.

6. The MOS transistor of claim 4 wherein the third doped region has a peak doping concentration that is greater than a peak doping concentration of the second doped region.

7. The MOS transistor of claim 3 wherein the second doped region is coupled to a first conductor and the body region is electrically coupled to a second conductor that is not directly connected to the first conductor.

8. A method of forming an MOS transistor comprising:

providing a substrate having a first conductivity type and having a first surface;

forming a first doped region of a second conductivity type within at least a portion of the substrate and having a first peak doping concentration;

forming a second doped region of the first conductivity type overlying at least a portion of the first doped region and having a second peak doping that is no greater than the first peak doping concentration;

forming a third doped region of the first conductivity type overlying at least a portion of the second doped region and having a third peak doping concentration that is greater than the second peak doping concentration; and

forming an opening into the substrate with the opening having a sidewall juxtaposed to the first doped region and the second doped region.

9. The method of claim 8 further including forming a first insulator having a first thickness along at least a first portion of the sidewall juxtaposed to the first doped region, and forming a second insulator having a second thickness along at least a second portion of the sidewall juxtaposed to the second doped region wherein the second thickness is greater than the first thickness.

10. The method of claim 8 wherein forming the third doped region of the first conductivity type overlying at least the portion of the second doped region includes forming the third doped region spaced a first distance from the opening.

11. The method of claim 8 further including forming the MOS transistor having a first blocking junction that blocks voltage applied in a first direction across the MOS transistor and a second blocking junction that blocks voltages applied in a second direction across the MOS transistor.

12. The method of claim 8 wherein forming the second doped region includes forming the second peak doping concentration less than the first peak doping concentration.

13. The method of claim 12 further including forming the second peak doping concentration no greater than approximately 5E17 atoms/cm³.

14. The method of claim 12 wherein forming the third doped region includes forming the third peak doping concentration greater than the first peak doping concentration and the second peak doping concentration.

15. The method of claim 14 wherein forming the third doped region includes forming the third peak doping concentration no less than approximately 1E18 atoms/cm³.

16. A method of forming an MOS transistor comprising:

forming a channel region having a first conductivity type and having a first peak doping concentration;

forming a current carrying region of a second conductivity type overlying the channel region and having a second peak doping concentration that is no greater than the first peak doping concentration;

forming a first doped region overlying the current carrying region and having a third peak doping concentration; and

forming a trench gate structure having a first insulator of a first thickness juxtaposed to the channel region and having a second insulator of a greater thickness juxtaposed to a portion of the current carrying region.

17. The method of claim 16 wherein forming the trench gate structure includes forming the second insulator as a layer of a first dielectric along a sidewall of an opening within a semiconductor substrate and forming a second dielectric on the first dielectric.

18. The method of claim 16 wherein forming the trench gate structure includes forming a first dielectric along a sidewall of an opening within a semiconductor substrate and increasing a thickness of the first dielectric along a second portion of the sidewall that is juxtaposed to the current carrying region.

19. The method of claim 16 further including forming a first conductor of a first resistivity within the trench gate structure and adjacent to the first insulator, and forming a second conductor of a second resistivity within the first conductor wherein the second resistivity is less than the first resistivity.

20. The method of claim 16 wherein forming the current carrying region includes forming the second peak doping concentration of the current carrying region to have a lower doping concentration than the third peak doping concentration of the first doped region and the first peak doping concentration of the channel region.

21. A method of forming an MOS transistor comprising:

providing a semiconductor substrate of a first conductivity type having a first surface;

forming a channel region of a second conductivity type on the first surface;

forming a current carrying region of the first conductivity type overlying the channel region;

forming a trench gate structure extending from the first surface into the channel region and having a insulator of a first thickness juxtaposed to the channel region;

forming a first conductor within the trench gate structure adjacent to the insulator; and

forming a second conductor within the trench gate structure electrically connected to the first conductor wherein the second conductor has a lower resistivity than the first conductor.

22. The method of claim 21 wherein forming the first conductor includes forming a conductor comprising silicon.

23. The method of claim 21 wherein forming the second conductor includes forming a metal-silicon alloy.