APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION OF A PROCESSOR BY ESTIMATING ENGINE LOAD

• US 20070208962A1
• Filed: 11/02/2006
• Published: 09/06/2007
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Zdravkovic, Andrej
• Granted Patent: US 7,610,499 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system has a processor and a queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of different clock frequencies. In one embodiment, the clocking frequency is determined by estimating a short or long term load associated with the stored instructions. In another embodiment, the clocking frequency is determined by analyzing a set of the stored instructions.

Claims

1. A method for reducing power consumption of at least one processor, the at least one processor is associated with at least one queue for storing instructions, the method comprising:

providing a series of instructions stored in the at least one queue;

estimating a short or long term load associated with the series of instructions;

selecting a clock rate out of a plurality of clocking rates based on in part the estimated short or long term load; and

clocking the at least one processor at the selected clock rate.

2. The method of claim 1, wherein the at least one processor is a graphics processor.

3. The method of claim 1, wherein the short term load is associated with the series of instructions stored in the at least one queue on a chip including the at least one processor.

4. The method of claim 1, wherein the long term load is associated with the series of instructions stored in the at least one queue off a chip including the at least one processor.

5. The method of claim 1, wherein the selected clock rate is also based on the current draw of the at least one processor.

6. A system for reducing power consumption of at least one processor, the system comprising:

at least one queue having stored instructions;

a controller that estimates a short or long term load associated with a series of instructions stored in the at least one queue and selects a clock rate for a clock out of a plurality of clocking rates based on in part the estimated short or long term load; and

the clock clocking the at least one processor at the selected clock rate.

7. The system of claim 6, wherein the at least one processor is a graphics processor.

8. The system of claim 6, wherein the short term load is associated with the series of instructions stored in the at least one queue on a chip including the at least one processor.

9. The system of claim 6, wherein the long term load is associated with the series of instructions stored in the at least one queue off a chip including the at least one processor.

10. The system of claim 6, wherein the selected clock rate is also based on the current draw of the at least one processor.

11. A method for reducing power consumption of at least one processor, the at least one processor is associated with at least one queue storing instructions for execution by the at least one processor, the method comprising:

estimating a load by at least analyzing a set of instructions stored in the at least one queue;

selecting a clock rate out of a plurality of clocking rates based on in part the estimated load; and

clocking the at least one processor at the selected clock rate.

12. The method of claim 11, wherein the analyzing the set of instructions includes determining a moving average of an intensity of instructions in the set of instructions.

13. The method of claim 11, wherein the analyzing the set of instructions includes determining a queue latency of the at least one queue.

14. The method of claim 11, further comprising:

grouping the set of instructions into at least one fuzzy set based on the estimated load;

outputting a fuzzy variable based on the at least one fuzzy set; and

selecting a clock rate out of a plurality of clocking rates based on in part the fuzzy variable.

15. The method of claim 11, wherein the at least one queue is on a chip including the at least one processor.

16. A system for reducing power consumption of at least one processor, the system comprising:

a clock adjustment device that estimates a load by at least analyzing a set of instructions stored in at least one queue and selects a clock rate for a clock out of a plurality of clocking rates based on in part the estimated load;

wherein the clock adjustment device controls the clock such that the at least one processor is clocked at the selected clock rate.

17. The system of claim 16, wherein analyzing the set of instructions includes determining a moving average of an intensity of instructions in the set of instructions.

18. The system of claim 16, wherein the analyzing the set of instructions includes determining a queue latency of the at least one queue.

19. The system of claim 16, further comprising:

a fuzzy logic controller grouping the set of instructions into at least one fuzzy set based on the estimated load and outputting a fuzzy variable based on the at least one fuzzy set; and

selecting the clock rate for the clock out of a plurality of clocking rates based on in part the fuzzy variable.

20. The system of claim 16, wherein the at least one queue is on a chip including the at least one processor.