Multi-stream interface for parallel test processing

• US 20070208985A1
• Filed: 02/03/2006
• Published: 09/06/2007
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Reichert, Peter, Conner, George, Robertson, Craig
• Granted Patent: US 7,673,199 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.

Claims

1. A tester processing system comprising:

a test head;

a tester data bus in communication with the test head;

a multi-stream switch in communication with the tester data bus; and

a plurality of processors in communication with the multi-stream switch;

wherein each of the plurality of processors runs a separate instance of tester software, and wherein the multi-stream switch is designed to allow each instance of the test software to communicate with corresponding sections of the test head through the tester data bus without interfering with instances of the test software running on other processors.

2. The tester processing system according to claim 1, wherein one of the plurality of processors is a primary processor having a user interface and wherein the primary processor can be used for single processor test operations.

3. The tester processing system according to claim 1 wherein the multi-stream switch converts streams from the plurality of processors to a protocol usable with test equipment that is designed for communication with a single processor.

4. The tester processing system according to claim 1 wherein the test head comprises one or more instrument slots and wherein each instance of the test software is assigned to one or more portions of corresponding instrument slots.

5. A multi-stream switch comprising:

a tester port;

a plurality of processor ports; and

protocol circuitry in communication with the tester port and in communication with the plurality of processor ports, wherein the protocol circuitry is designed to direct streams between each of the plurality of processor ports and the tester port.

6. The multi-stream switch according to claim 5, further comprising an electrical-optical interface converter in communication with the tester data bus port for optical communication with a test head.

7. The multi-stream switch according to claim 5, wherein the protocol circuitry comprises:

tester-side serializer/de-serializer circuitry in communication with the tester port;

tester data bus write circuitry in communication with the tester-side serializer/de-serializer circuitry;

tester data bus read circuitry in communication with the tester-side serializer/de-serializer circuitry;

a plurality of send processors in communication with the tester data bus write circuitry and the tester data bus read circuitry; and

corresponding processor-side read circuitry, processor-side write circuitry and processor-side serializer/de-serializer circuitry in communication with each of the processor ports and with a corresponding send processor of the plurality of send processors.

8. The multi-stream switch according to claim 7, wherein the tester-side serializer/de-serializer circuitry is designed to convert between serial data and parallel data between a test head and the send processors.

9. The multi-stream switch according to claim 7, wherein the tester data bus write circuitry and tester data bus read circuitry is designed to provide throttling into the send processors, build multi-stream read/write frames based on pending data from the send processors, dismantle multi-stream frames and send dismantled multi-stream frames to the send processors.

10. The multi-stream switch according to claim 7, wherein the send processors are designed to buffer and throttle reads and writes coming from the plurality of processors, connect read data from the test head back to read requests from the processor, send data back to the processors, buffer write data to the test head and buffer read data from the test head.

11. The multi-stream switch according to claim 7, further comprising a token store in communication with the plurality of send processors.

12. The multi-stream switch according to claim 11, wherein the plurality of send processors are designed to indicate a packet type of a packet in a stream, request tokens for shared resources and dismantle single stream frames.

13. A method for testing a device, comprising:

connecting at least one portion of at least one instrument slot to a multi-stream switch through a tester data bus;

connecting a plurality of processors to the multi-stream switch through a plurality of processor data buses; and

running separate instances of tester software on the plurality of processors.

14. The method according to claim 13 further comprising converting streams from the plurality of processor data buses to streams suitable for the tester data bus.

15. The method according to claim 13 further comprising converting streams from the tester data bus to streams suitable for the plurality of processor data buses.

16. The method according to claim 13 further comprising communicating with a test head using a protocol that appears to the test head to be from a single processor, so as not to require modification of test equipment or software that was designed for operation with a single processor.

17. A method for interfacing a plurality of processors to a single test head comprising buffering and steering multiple streams between the plurality of processors and the single test head.

18. The method according to claim 17, further comprising constructing extended frames which include stream identifying information and which appear to the test head to be standard tester protocol frames.

19. The method according to claim 18, further comprising identifying the streams by a stream number in the extended frames.

20. The method according to claim 18, further comprising identifying the streams by their position in the extended frames.