Charge storage structure formation in transistor with vertical channel region

• US 20070210338A1
• Filed: 03/08/2006
• Published: 09/13/2007
• Est. Priority Date: 03/08/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Orlowski, Marius
• Granted Patent: US 7,535,060 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Claims

1. A semiconductor device, comprising:

a semiconductor structure having a first sidewall and a channel region, wherein a portion of said channel region is disposed along said first sidewall, and wherein the channel region is disposed between first and second current electrode regions;

first and second charge storage structures disposed adjacent to the first sidewall and adjacent to the portion of the channel region disposed along the first sidewall, wherein the first and second charge storage structures are electrically isolated from each other and from the semiconductor structure; and

a first control electrode formed adjacent to the first sidewall.

2. The semiconductor device of claim 1, wherein the semiconductor device fisher comprises:

third and fourth charge storage structures located adjacent to the second sidewall, wherein the third and fourth charge storage structures are electrically isolated from each other and are electrically isolated from the semiconductor structure.

3. The semiconductor device of claim 2, further comprising a second control electrode disposed adjacent to the second sidewall, wherein the second control electrode is electrically independent from the first control electrode.

4. The semiconductor device of claim 1, wherein each of the first and second charge storage structures comprises germanium.

5. The semiconductor device of claim 1, further comprising:

a first dielectric layer formed adjacent to the first sidewall;

a second dielectric layer formed adjacent to the first dielectric layer; and

a third dielectric layer formed adjacent to the second dielectric layer;

wherein the first, second, and third dielectric layers provide electrical isolation for the first charge storage structure and the second charge storage structure;

wherein the second dielectric layer has first and second openings therein, and wherein the first charge storage structure is formed within the first opening and the second charge storage structure is formed within the second opening.

6. The semiconductor device of claim 5, wherein the first and second dielectric layers respectively comprise first and second distinct materials.

7. The semiconductor device of claim 1, wherein the first and second charge storage structures are floating gate charge storage structures.

8. The semiconductor device of claim 1 further comprising:

a first dielectric layer disposed between the control electrode and the first sidewall;

a second dielectric layer disposed between the control electrode and the first dielectric layer; and

a third dielectric layer disposed between the first dielectric layer and the second dielectric layer;

wherein a portion of the third dielectric layer is laterally disposed between the first charge storage structure and the second charge storage structure.

9. The semiconductor device of claim 8 wherein:

the first dielectric layer has a first lateral length L₁ in a first direction along the first sidewall;

the second dielectric layer has a second lateral length L₂ in a direction parallel to the first direction; and

the third dielectric layer has a third lateral length L₃ in a direction parallel to the first direction;

wherein L₃<

L₁, L₂.

10. The semiconductor device of claim 1, wherein the semiconductor structure is a semiconductor fin structure.

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