Power semiconductor device

• US 20070210356A1
• Filed: 03/07/2007
• Published: 09/13/2007
• Est. Priority Date: 03/07/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Henson, Timothy
• Granted Patent: US 7,554,153 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device which includes an implant region in the base region thereof to reduce Qgd.

Claims

1. A power semiconductor device comprising:

a semiconductor body having a common conduction region of one conductivity, and a base region of another conductivity, said semiconductor body including a first surface;

a trench extending from said first surface through said base region and into said common conduction region, said trench including at least two opposing sidewalls and a bottom;

a first gate insulation adjacent one of said sidewalls;

a first gate electrode adjacent said first gate insulation and spanning said base region;

a source region adjacent at last one sidewall of said trench;

a source contact electrically connected to said source regions; and

a Qgd implant region of said another conductivity in said base region to vary the resistivity of said base region, whereby the resistivity of said base region adjacent said first gate insulation is higher than the resistivity of said Qgd implant region and said Qgd implant is positioned to retard the encroachment of the depletion region into said base region without varying the threshold voltage of the device.

2. A semiconductor device according to claim 1, further comprising:

a second gate insulation adjacent the other of said sidewalls;

a second gate electrode adjacent said second gate insulation and spanning said base region;

a source field electrode having a first portion and a second portion, said first portion of said source field electrode being disposed between said first and said second gate electrodes and insulated from the same by an insulation body, and said second portion of said source field electrode being disposed below said first portion and said gate electrodes, wherein said source contact is electrically connected to said source field electrode.

3. A semiconductor device according to claim 2, further comprising a first insulation cap interposed between said source contact and said first gate electrode and a second insulation cap interposed between said source contact and said second gate electrode, wherein said source field electrode is disposed between said first insulation cap and said second insulation cap.

4. A semiconductor device according to claim 2, wherein said source field electrode extends out of said trench and above said first surface of said semiconductor body.

5. A semiconductor device according to claim 2, further comprising a bottom insulation body disposed between said second portion of said source field electrode and said sidewalls and said bottom of said trench.

6. A semiconductor device according to claim 5, wherein said bottom insulation body is thicker than said gate insulations.

7. A semiconductor device according to claim 5, wherein said bottom insulation body is disposed below both gate electrodes.

8. A semiconductor device according to claim 2, wherein said source field electrode is comprised of conductive polysilicon.

9. A semiconductor device according to claim 2, wherein said gate electrodes are comprised of conductive polysilicon.

10. A semiconductor device according to claim 1, wherein said semiconductor body is comprised of epitaxial silicon.

11. A semiconductor device according to claim 9, wherein said epitaxial silicon is formed over a silicon substrate, and further comprising a drain contact ohmically connected to said silicon substrate.

12. A semiconductor device according to claim 2, wherein a top surface of said source field electrode is coplanar with top surfaces of said gate electrodes.

13. A MOSgated power semiconductor device comprising:

an active area including at least one active cell, said active cell including at least one source region, a source contact electrode connected to said source region, an insulated gate electrode, a base region of one conductivity formed adjacent a drift region of another conductivity, and a Qgd implant of the same conductivity as said base region formed in said base region and spaced from said insulated gate electrode, wherein the resistivity and the position of said Qgd implant region are selected to hinder the movement of a depletion region into said base region without affecting the threshold voltage of the device.

14. A device according to claim 13, further comprising an insulated source field electrode extending below said insulated gate electrode and electrically connected to said source contact.

15. A device according to claim 14, wherein said source field electrode extends to a height above said insulated gate electrode.

16. A device according to claim 13, further comprising a drain contact disposed opposite said source contact.

17. A device according to claim 14, wherein a top surface of said source field electrode is coplanar with a top surface of said gate electrode.