CMOS imager with selectively silicided gate

• US 20070210360A1
• Filed: 05/08/2007
• Published: 09/13/2007
• Est. Priority Date: 08/16/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Howard Rhodes
• Inventors: Rhodes, Howard
• Granted Patent: US 7,405,101 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Claims

1-86. -86. (canceled)

87. A method of forming an imager, comprising:

forming an array of pixel cells comprising;

forming a plurality of gates;

forming a silicide on at least a portion of said plurality of gates; and

removing said silicide from at least a portion of at least one of said plurality of gates.

88. The method of claim 87, wherein forming said plurality of gates includes forming a photogate and said removing act comprises removing said silicide from at least a portion of said photogate.

89. The method of claim 88, wherein said removing act comprises retaining at least a portion of said silicide on said photogate.

90. The method of claim 88, wherein said removing act comprises retaining at least a portion of said silicide on at least one of said plurality of gates.

91. The method of claim 88, wherein forming said plurality of gates further includes forming at least one of a transfer gate, a reset gate, and a source follower gate.

92. The method of claim 87, further comprising:

providing a light-shielding material over said plurality of gates; and

forming openings through said light-shielding material, said openings corresponding to and positioned over said plurality of gates.

93. The method of claim 92, further comprising:

forming a transparent insulating layer over said plurality of gates; and

forming contact holes within said transparent insulating layer, said contact holes corresponding to and positioned over each of said plurality of gates except for said photogate, wherein said transparent insulating layer fills the one of said plurality of openings corresponding to and positioned over said photogate.

94. A method of forming a pixel cell, comprising:

forming a polysilicon layer over a substrate comprising a doped region;

forming a photogate insulator over said doped region;

forming a metal layer over said photogate insulator and said polysilicon;

forming a silicide from a first portion of said metal layer over said polysilicon layer;

removing a second portion of said metal layer over said photogate insulator, wherein said removing act comprises retaining said silicide over said polysilicon layer;

forming a first gate over said doped region from said polysilicon layer; and

forming a second gate from said silicide and said polysilicon layer.