SEMICONDUCTOR MEMORY DEVICE

• US 20070210418A1
• Filed: 03/01/2007
• Published: 09/13/2007
• Est. Priority Date: 03/09/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAKAJIMA, Hiroomi
• Application Number:
  US11/680,931
• Publication Number:
  US 20070210418A1
• Time in Patent Office: Days
• US Class Current: 257/547
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A memory includes a semiconductor layer provided on an insulation film provided on a first conductivity type substrate; a first well of a second conductivity type provided in the substrate; second wells of the first conductivity type provided in the first well; a third well of a second conductivity type provided in the substrate; a memory cell including a first source, a first drain and a body region, the first source and drain being formed in the semiconductor layer located above one of the second wells; a first logic circuit including a second source, a second drain and a channel region, the second source and drain being formed on the semiconductor layer above another one of the second wells; and a second logic circuit including a third source, a third drain and a channel region, the third source and drain being formed on the semiconductor layer above the third well.

Claims

1. A semiconductor memory device comprising:

a support substrate including a first conductivity type semiconductor;

an insulation film provided on the support substrate;

a semiconductor layer provided on the insulation film;

a first well of a second conductivity type provided in the support substrate;

second wells of the first conductivity type provided in the first well;

a third well of a second conductivity type provided in the support substrate;

a memory cell including a first source of the second conductivity type, a first drain of the second conductivity type and a body region formed between the first source and the first drain, the first source and the first drain being formed in the semiconductor layer located above one of the second wells, the body region being in an electrically floating state and accumulating or emitting charges for storing therein data;

a first logic circuit element including a second source of the second conductivity type, a second drain of the second conductivity type and a channel region of the first conductivity type formed between the second source and the second drain, the second source and the second drain being formed on the semiconductor layer above another one of the second wells; and

a second logic circuit element including a third source of the first conductivity type, a third drain of the first conductivity type and a channel region of the second conductivity type formed between the third source and the third drain, the third source and the third drain being formed on the semiconductor layer above the third well.

2. The semiconductor memory device according to claim 1, wherein the body region is the first conductivity type.

3. The semiconductor memory device according to claim 1, wherein the second well is used for a back bias gate.

4. The semiconductor memory device according to claim 2, wherein the second well is used for a back bias gate.

5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a memory-logic integrated semiconductor memory device having the memory cell, the first logic circuit element, and the second logic circuit element provided on a same substrate.

6. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a memory-logic integrated semiconductor memory device having the memory cell, the first logic circuit element, and the second logic circuit element provided on a same substrate.

7. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a memory-logic integrated semiconductor memory device having the memory cell, the first logic circuit element, and the second logic circuit element provided on a same substrate.

8. The semiconductor memory device according to claim 1, wherein the first well is connected to a voltage source different from a voltage of the second well and from a voltage of the support substrate.

9. The semiconductor memory device according to claim 1, wherein the thickness of the insulation film is equal to or less than 50 nm.

10. The semiconductor memory device according to claim 1, wherein the memory cell is a floating body cell.

11. A method of manufacturing a semiconductor memory device comprising:

preparing a semiconductor substrate including a support substrate including a first conductivity type semiconductor, an insulation film provided on the support substrate, and a semiconductor layer provided on the insulation film;

forming a first well of a second conductivity type in the support substrate;

forming second wells of the first conductivity type in the first well;

forming a third well of the first conductivity type in the support substrate; and

forming a first source of the second conductivity type and a first drain of the second conductivity type in the semiconductor layer above one of the second well, a second source of the second conductivity type and a second drain of the second conductivity type in the semiconductor layer above another one of the second well, and a third source of the first conductivity type and a third drain of the first conductivity type in the semiconductor layer above the third well, wherein

the semiconductor layer between the first source and the first drain is used as a body region of the first conductivity type which is in an electrically floating state and accumulates or emits charges for storing therein data,

the semiconductor layer between the second source and the second drain is used as a channel region of the first conductivity type, and

the semiconductor layer between the third source and the third drain is used as a channel region of the second conductivity type.

12. The method of manufacturing a semiconductor memory device according to claim 11, wherein the second well is used for a back bias gate.

13. The semiconductor memory device according to claim 11, wherein the memory cell, the first logic circuit element, and the second logic circuit element are formed on a same die.

14. The semiconductor memory device according to claim 11, wherein the thickness of the insulation film is equal to or less than 50 nm.

15. The semiconductor memory device according to claim 11, wherein the memory cell is a floating body cell.