Three dimensional integrated circuits

• US 20070210830A1
• Filed: 05/11/2007
• Published: 09/13/2007
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Tier Logic, Inc.
• Inventors: Madurawe, Raminda
• Granted Patent: US 7,362,133 B2
• Time in Patent Office: Days
• US Class Current: 326/47
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.

Claims

1. A three-dimensional semiconductor device, comprising:

a programmable logic circuit; and

a configuration circuit comprising a memory element, wherein;

the memory element is positioned above the logic circuit; and

the memory element is coupled to the logic circuit to program the logic circuit.

2. The device of claim 1, wherein the memory element comprises one or more devices selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, thin film transistor (TFT).

3. The device of claim 1, wherein the memory element is selected from the group consisting of volatile or non volatile memory elements.

4. The device of claim 1, wherein the memory element is selected from a group of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, voltage modulating element, and ferro-electric elements.

5. The device of claim 1, wherein the configuration circuit further comprises a redundant memory element coupled to the same logic circuit.

6. The device of claim 1, wherein the logic circuit further comprises a redundant logic element coupled to the same memory element.

7. The device of claim 1, wherein the programmable logic circuit responds to input signals and develop corresponding complete or partial output logic signals.

8. The device of claim 1, wherein the programmable logic circuit comprises registers to store output logic signals.

9. The device of claim 8, comprising a clock signal and a control signal.

10. The device of claim 1, wherein the programmable logic circuit comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, OR logic, arithmetic logic, carry logic, floating point logic, and any other logic.

11. A three-dimensional semiconductor device, comprising:

a first module layer having a circuit block; and

a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.

12. The device of claim 11, wherein the configuration circuit comprises a memory element comprising one or more devices selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, thin film transistor (TFT).

13. The device of claim 12, wherein the memory element is selected from the group consisting of volatile or non volatile memory elements.

14. The device of claim 12, wherein the memory element is selected from a group of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, voltage modulating element, and ferro-electric elements.

15. The device of claim 11, wherein the logic block comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, OR logic, arithmetic logic, carry logic, floating point logic, and any other logic.

16. A three-dimensional semiconductor device, wherein:

a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit.

17. The device of claim 16, wherein the configurable memory element comprises one or more devices selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, thin film transistor (TFT).

18. The device of claim 17, wherein the configurable memory element is selected from the group consisting of volatile or non volatile memory elements.

19. The device of claim 17, wherein the configurable memory element is selected from a group of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, voltage modulating element, and ferro-electric elements.

20. The device of claim 16, wherein a said programmable logic circuit comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, OR logic, arithmetic logic, carry logic, floating point logic, and any other logic.