×

Semiconductor memory device

  • US 20070211528A1
  • Filed: 03/14/2007
  • Published: 09/13/2007
  • Est. Priority Date: 09/14/2004
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:

  • a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged successively in rows;

    a plurality of word lines, each word line being coupled to the gate electrodes of the selection transistors in a respective row;

    a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors, no two of which are arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and

    a plurality of memory elements formed as resistance memory elements, the memory elements being coupled row by row to read/write lines, each memory element being coupled between a respective read/write line and that source/drain region of a selection transistor that is not coupled to a bit line, wherein two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×