Semiconductor memory device
First Claim
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1. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:
- a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged successively in rows;
a plurality of word lines, each word line being coupled to the gate electrodes of the selection transistors in a respective row;
a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors, no two of which are arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and
a plurality of memory elements formed as resistance memory elements, the memory elements being coupled row by row to read/write lines, each memory element being coupled between a respective read/write line and that source/drain region of a selection transistor that is not coupled to a bit line, wherein two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.
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Abstract
A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.
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Citations
20 Claims
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1. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:
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a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged successively in rows;
a plurality of word lines, each word line being coupled to the gate electrodes of the selection transistors in a respective row;
a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors, no two of which are arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and
a plurality of memory elements formed as resistance memory elements, the memory elements being coupled row by row to read/write lines, each memory element being coupled between a respective read/write line and that source/drain region of a selection transistor that is not coupled to a bit line, wherein two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification