Nonvolatile memory device and related programming method
First Claim
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1. A nonvolatile memory device, comprising:
- a memory cell array comprising memory cells selected by word lines and bit lines;
a row decoder circuit providing a program voltage to a selected word line;
a first verification circuit providing a first verification result indicating whether or not memory cells in a predetermined bit unit and programmed by the program voltage are successfully programmed;
a second verification circuit providing a second verification result indicating whether or not a far cell within the predetermined bit unit is successfully programmed;
a controller defining a level and an application time for a program voltage applied during a next program loop in response to the first and second verification results;
a word line voltage generating circuit generating the program voltage; and
a word line driver supplying the program voltage to the row decoder during the next program loop.
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Abstract
In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.
58 Citations
16 Claims
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1. A nonvolatile memory device, comprising:
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a memory cell array comprising memory cells selected by word lines and bit lines; a row decoder circuit providing a program voltage to a selected word line; a first verification circuit providing a first verification result indicating whether or not memory cells in a predetermined bit unit and programmed by the program voltage are successfully programmed; a second verification circuit providing a second verification result indicating whether or not a far cell within the predetermined bit unit is successfully programmed; a controller defining a level and an application time for a program voltage applied during a next program loop in response to the first and second verification results; a word line voltage generating circuit generating the program voltage; and a word line driver supplying the program voltage to the row decoder during the next program loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for programming a non-voltage memory device having memory cells selected by word lines and bit lines, the method comprising:
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applying a program voltage to a selected word line through a row decoder; verifying whether or not memory cells in a predetermined bit unit programmed by the program voltage are successfully programmed and providing a corresponding first verification result; verifying whether or not a far cell amongst the memory cells in the predetermined bit unit is successfully programmed and providing a corresponding second verification result; and adjusting a level and application time for a program voltage applied during a next program loop in response to the first and second verification results. - View Dependent Claims (13, 14, 15, 16)
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Specification