SEMICONDUCTOR WAFER ANALYSIS SYSTEM

• US 20070211932A1
• Filed: 12/29/2006
• Published: 09/13/2007
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Chang-Huhn, HONG, Seok-Woo
• Granted Patent: US 8,009,895 B2
• Time in Patent Office: Days
• US Class Current: 382/145
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection

Abstract

A semiconductor wafer analysis system is provided. In an embodiment, the semiconductor wafer analysis system includes a tester to test semiconductor wafers manufactured by at least one manufacturing facility, a wafer map generation module to generate wafer maps on the basis of the test results from the tester, and a wafer analysis module. The wafer analysis module may include a data generation module that divides each wafer map into a plurality of defect analysis regions and generates feature vectors representing the semiconductor wafers, and an operation module that statistically analyzes the feature vectors.

Claims

1. A semiconductor wafer analysis system comprising:

a tester adapted to output test results responsive to a test of presence and type of defects on semiconductor wafers manufactured by at least one manufacturing facility;

a wafer map generation module adapted to generate wafer maps based on the test results from the tester; and

a wafer analysis module including a data generation module and an operation module, the data generation module adapted to divide each wafer map into a plurality of defect analysis regions and to generate feature vectors representing the semiconductor wafers, and the operation module adapted to statistically analyze the feature vectors so as to assist in the determination of a defective one or more of the manufacturing facilities.

2. The semiconductor wafer analysis system of claim 1, wherein a plurality of component values of the feature vectors are defect values that represent at least one defect type occurring in each defect analysis region.

3. The semiconductor wafer analysis system of claim 2, wherein the defect types are category type defects, and the defect values are incidences of the category type defects in the defect analysis regions.

4. The semiconductor wafer analysis system of claim 2, wherein the defect types are parameter type defects, and the defect values are mean values of the parameter values.

5. The semiconductor wafer analysis system of claim 1, wherein the operation module is adapted to perform analyses of variance of the feature vectors to determine which of a plurality of manufacturing facilities cause defects to occur in a specific defect analysis region of the semiconductor wafers.

6. The semiconductor wafer analysis system of claim 5, wherein an ANOVA method is used as the analysis of variance.

7. The semiconductor wafer analysis system of claim 2, wherein the operation module, using a clustering method, is adapted to cluster the feature vectors to classify the feature vectors based on the defect types, and to determine whether a specific kind of defect occurs in each manufacturing facility.

8. The semiconductor wafer analysis system of claim 7, wherein a k-means clustering algorithm, a self-organizing map clustering algorithm, or a hierarchical clustering algorithm is used as the clustering method.

9. The semiconductor wafer analysis system of claim 7, wherein a chi-square analysis method is used to determine whether a specific kind of defect occurs in each manufacturing facility.

10. The semiconductor wafer analysis system of claim 1, wherein each of the defect analysis regions includes at least one chip die.

11. A semiconductor wafer analysis system comprising:

a tester to test semiconductor wafers manufactured by at least one manufacturing facility;

a wafer map generation module to generate wafer maps based on test results from the tester; and

a wafer analysis module that includes a data generation module and an operation module,

wherein the data generation module is adapted to divide each wafer map into a plurality of defect analysis regions and to generates feature vectors representing the semiconductor wafers, and

the operation module is adapted to classify the feature vectors into clusters based on defect type by k-means clustering, and to determine whether a specific kind of defect occurs in each manufacturing facility by a chi-square analysis method.

12. The semiconductor wafer analysis system of claim 11, wherein a plurality of component values of the feature vectors are defect values representing at least one of the defect types occurring in each defect analysis region.

13. The semiconductor wafer analysis system of claim 12, wherein the defect types are category type defects, and the defect values represent the category type defects in the defect analysis regions.

14. The semiconductor wafer analysis system of claim 12, wherein the defect types are parameter type defects, and the defect values are mean values of parameter values of the semiconductor wafers.

15. The semiconductor wafer analysis system of claim 11, wherein each of the defect analysis regions includes a plurality of chip dies.

16. A semiconductor wafer analysis system comprising:

a tester for yielding test results by testing semiconductor wafers manufactured by two or more one manufacturing facilities;

a wafer map generation module for generating wafer maps based on the test results; and

a wafer analysis module for dividing each wafer map into a plurality of defect analysis regions and for statistically analyzing data of each defect analysis region.

17. The semiconductor wafer analysis system of claim 16, wherein the wafer analysis module is adapted to determine whether a specific one of the two or more manufacturing facilities causes defects to occur in the defect analysis regions by statistically analyzing the data of each defect analysis region.

18. The semiconductor wafer analysis system of claim 16, wherein the plurality of defect analysis regions include a plurality of chip dies.

19. A semiconductor wafer analysis method, comprising:

testing semiconductor wafers manufactured by at least one manufacturing facility;

generating wafer maps based on the testing;

dividing each wafer map into a plurality of defect analysis regions; and

statistically analyzing data of each of the defect analysis regions.

20. The semiconductor wafer analysis method of claim 19, further comprising determining whether a specific manufacturing facility of the at least one manufacturing facility causes defects to occur in the defect analysis regions of the wafers based on the statistical analyzing step.

21. The semiconductor wafer analysis method of claim 20, wherein the determining step includes, for each manufacturing facility, performing a chi-square analysis on feature vector clusters from the data.

22. The semiconductor wafer analysis method of claim 20, wherein the determining step includes, for each manufacturing facility, using an ANOVA (Analysis of Variance) method for analysis of variance of the data.

23. The semiconductor wafer analysis method of claim 19, further including the step of generating feature vectors having defect values, which represent at least one defect type occurring in each defect analysis region, as a plurality of component values.

24. The semiconductor wafer analysis method of claim 23, further comprising the step of clustering a plurality of feature vectors to classify the feature vectors on the basis of the defect type.

25. The semiconductor wafer analysis method of claim 24 wherein the step of clustering a plurality of feature vectors includes using algorithms taken from a group consisting of a k-means clustering algorithm, a self-organizing map clustering algorithm, and a hierarchical clustering algorithm.