MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS

• US 20070212810A1
• Filed: 05/15/2007
• Published: 09/13/2007
• Est. Priority Date: 05/31/2005
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Charles Koburger, Chung Lam, David Horak, Gerhard Meijer, Mark Hakey, Steven Holmes, Toshijaru Furukawa
• Inventors: Holmes, Steven, Horak, David, Furukawa, Toshijaru, Hakey, Mark, Meijer, Gerhard, Lam, Chung, Koburger, Charles
• Granted Patent: US 7,378,678 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: Y10S 438/90 Bulk effect device making

Abstract

Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

Claims

1. A method of forming a memory device, said method comprising:

simultaneously forming a series of single memory cells, wherein forming of each of said single memory cells in said series comprises;

forming two parallel holes in an insulating layer;

forming a memory element with a first top electrical contact in one of said two parallel holes by filling said one of said two parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer,

forming a conductive section with a second top electrical contact in another of said two parallel holes by filling said other of said two parallel holes with a conductive material; and

electrically connecting said memory element and said conductive section;

simultaneously conditioning all of said transition metal oxide layers of said memory elements of said single memory cells in said series,

wherein said conditioning causes said transition metal oxide layers to exhibit a bi-stable electrical resistance.

2. The method of claim 1, wherein said process of simultaneously conditioning all of said transition metal oxide layers comprises:

connecting said first top electrical contacts of said memory elements of each of said single memory cells in said series to said second top electrical contacts of said conductive sections of an adjacent single memory cell in said series with a temporary conductor,

connecting said temporary conductor at an end of said series to a power source adapted to output a current through said series of said single memory cells.

3. The method of claim 2, further comprising:

reducing the voltage from said power source as said transition metal oxide layer of each of said single memory cells in said series is conditioned.

4. The method of claim 3, further comprising:

removing said temporary conductor after conditioning said transition metal oxide layer of said memory element of all of said single memory cells in said series.

5. The method of claim 1, further comprising:

electrically connecting said single memory cells in said series using a cross point wire array.

6. A method of forming a memory device, said method comprising:

simultaneously forming a series of double memory cells, wherein forming of each of said double memory cells in said series comprises;

forming three parallel holes in an insulator layer;

forming a first memory element with a first top electrical contact and a second memory element with a second top electrical contact in two of said three parallel holes by filling said two of said three parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer,

forming a conductive section with a third top electrical contact in another of said three parallel holes by filling said other of said three parallel holes with a conductive material; and

electrically connecting said conductive section to each of said first memory element and said second memory element;

simultaneously conditioning said transition metal oxide layer of said first memory element of each of said double memory cells in said series; and

simultaneously conditioning said transition metal oxide layer of said second memory element of each of said double memory cells in said series,

wherein said conditioning causes said transition metal oxide layers to exhibit a bi-stable electrical resistance.

7. The method of claim 6, wherein said process of simultaneously conditioning said transition metal oxide layer of said first memory element comprises:

connecting said first top electrical contacts from said double memory cells in said series to said third top electrical contact of an adjacent double memory cell in said series with a temporary conductor;

connecting said temporary conductor at an end of said series to a power source adapted to output a electric current;

reducing the voltage output from said power source as each of said transition metal oxide layers of said first memory element from each of said double memory cells is conditioned; and

removing said temporary conductor after conditioning said transition metal oxide layer of said first memory element of all of said double memory cells in said series.

8. The method of claim 7, wherein said process of simultaneously conditioning said transition metal oxide layer of said second memory element comprises, after said process of simultaneously conditioning said transition metal oxide layer of said first memory element,

connecting said second top electrical contact from each of said double memory cells in said series to said third top electrical contact of an adjacent double memory cell in said series with a temporary conductor;

connecting said temporary conductor at an end of said series to a power source adapted to output a electric current;

reducing the voltage output from said power source as each of said transition metal oxide layers of said second memory element from each of said double memory cells is conditioned; and

removing said temporary conductor after conditioning said transition metal oxide layer of said second memory element of all of said double memory cells in said.

9. The method of claim 8, further comprising:

electrically connecting said double memory cells in said series using a cross point wire array.

10. A method of forming a memory device, said method comprising:

simultaneously forming a single memory cell, wherein forming of said single memory cell comprises;

forming two parallel holes in an insulating layer;

forming a memory element with a first top electrical contact in one of said two parallel holes by filling said one of said two parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer,

forming a conductive section with a second top electrical contact in another of said two parallel holes by filling said other of said two parallel holes with a conductive material; and

electrically connecting said memory element and said conductive section;

conditioning said transition metal oxide layer of said single memory cell,

wherein said conditioning causes said transition metal oxide layer to exhibit a bi-stable electrical resistance.

11. The method of claim 10, wherein said process of conditioning said transition metal oxide layer comprises:

connecting first top electrical contacts of memory elements in a series of single memory cells to second top electrical contacts of conductive sections of an adjacent single memory cell in said series with a temporary conductor,

connecting said temporary conductor at an end of said series to a power source adapted to output a current through said series of said single memory cells.

12. The method of claim 11, further comprising:

reducing the voltage from said power source as said transition metal oxide layer of each of said single memory cells in said series is conditioned.

13. The method of claim 12, further comprising:

removing said temporary conductor after conditioning said transition metal oxide layer of said memory element of all of said single memory cells in said series.

14. The method of claim 10, further comprising:

electrically connecting said single memory cells in said series using a cross point wire array.

15. A method of forming a memory device, said method comprising:

simultaneously forming a single memory cell, wherein forming of said single memory cell comprises;

forming two parallel holes in an insulating layer;

forming a memory element with a first top electrical contact in one of said two parallel holes by filling said one of said two parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer,

forming a conductive section with a second top electrical contact in another of said two parallel holes by filling said other of said two parallel holes with a conductive material; and

electrically connecting said memory element and said conductive section;

conditioning said transition metal oxide layer of said single memory cell,

wherein said conditioning causes said transition metal oxide layer to exhibit a bi-stable electrical resistance;

electrically connecting said single memory cells in said series using a cross point wire array.

16. The method of claim 15, wherein said process of conditioning said transition metal oxide layer comprises:

connecting first top electrical contacts of memory elements in a series of single memory cells to second top electrical contacts of conductive sections of an adjacent single memory cell in said series with a temporary conductor,

connecting said temporary conductor at an end of said series to a power source adapted to output a current through said series of said single memory cells.

17. The method of claim 16, further comprising:

reducing the voltage from said power source as said transition metal oxide layer of each of said single memory cells in said series is conditioned.

18. The method of claim 17, further comprising:

removing said temporary conductor after conditioning said transition metal oxide layer of said memory element of all of said single memory cells in said series.