Integrated Circuit With Bulk and SOI Devices Connected with an Epitaxial Region

• US 20070212857A1
• Filed: 05/16/2007
• Published: 09/13/2007
• Est. Priority Date: 10/08/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Brent Anderson, Edward Nowak
• Inventors: Anderson, Brent, Nowak, Edward
• Granted Patent: US 7,682,941 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Claims

1-13. -13. (canceled)

14. A method for forming a semiconductor integrated circuit with an SOI region and a bulk region, comprising the steps of:

a) forming a substrate with and SOI region and a bulk region separated by an embedded sidewall spacer;

b) etching the sidewall spacer to form an empty trench; and

c) epitaxially depositing semiconductor material in the trench.

15. The method of claim 14 further comprising the steps of:

d) planarizing the wafer after step (c).

e) forming a first type doping in the bulk region, and a second type doping in the SOI region, wherein a P-N junction between the first type doping and the second type doping is disposed in the SOI region or in the trench.

16. The method of claim 15 further comprising the step of:

f) forming a metal silicide layer across the P-N junction after step (f).

17. The method of claim 14 wherein the sidewall spacer is completely removed in step (b).

18. The method of claim 14 wherein the sidewall spacer is partially removed in step (b).